On 3/16/20 1:40 PM, twar...@nvidia.com wrote: > From: JC Kuo <jc...@nvidia.com> > > This commit removes the programming sequence that enables PLLE and UPHY > PLL hardware power sequencers. Per TRM, boot software should enable PLLE > and UPHY PLLs in software controlled power-on state and should power > down PLL before jumping into kernel or the next stage boot software. > > Adds call to board_cleanup_before_linux to facilitate this.
This directly contradicts what's in Tegra_X1_TRM_DP07225001_v1.3p.pdf, pages 1340/1341, which is what the code currently implements. Was a newer internal-only TRM published that changed the recommended programming flow?
