Hi Bin, >-----Original Message----- >From: Bin Meng <bmeng...@gmail.com> >Sent: 13 March 2020 13:21 >To: Pragnesh Patel <pragnesh.pa...@sifive.com> >Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Atish Patra ><atish.pa...@wdc.com>; Palmer Dabbelt <palmerdabb...@google.com>; Paul >Walmsley <paul.walms...@sifive.com>; Jagan Teki ><ja...@amarulasolutions.com>; Troy Benjegerdes ><troy.benjeger...@sifive.com>; Anup Patel <anup.pa...@wdc.com>; Sagar >Kadam <sagar.ka...@sifive.com>; Rick Chen <r...@andestech.com> >Subject: Re: [PATCH v5 07/14] sifive: dts: fu540: Add DDR controller and phy >register settings > >On Wed, Mar 11, 2020 at 3:04 PM Pragnesh Patel ><pragnesh.pa...@sifive.com> wrote: >> >> Add DDR controller and phy register settings, taken from fsbl >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel <pragnesh.pa...@sifive.com> >> --- >> arch/riscv/dts/fu540-c000-u-boot.dtsi | 7 + >> arch/riscv/dts/fu540-sdram-ddr4.dtsi | 1489 +++++++++++++++++ >> .../dts/hifive-unleashed-a00-u-boot.dtsi | 1 + >> 3 files changed, 1497 insertions(+) >> create mode 100644 arch/riscv/dts/fu540-sdram-ddr4.dtsi >> >> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi >> b/arch/riscv/dts/fu540-c000-u-boot.dtsi >> index 2d3d62801f..b8cef67885 100644 >> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi >> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi >> @@ -40,6 +40,13 @@ >> reg = <0x0 0x2000000 0x0 0xc0000>; >> u-boot,dm-spl; >> }; >> + dmc: dmc@100b0000 { >> + compatible = "sifive,fu540-ddr"; >> + reg = <0x0 0x100b0000 0x0 0x0800 >> + 0x0 0x100b2000 0x0 0x2000 >> + 0x0 0x100b8000 0x0 0x0fff>; >> + u-boot,dm-spl; >> + }; >> }; >> }; >> >> diff --git a/arch/riscv/dts/fu540-sdram-ddr4.dtsi >> b/arch/riscv/dts/fu540-sdram-ddr4.dtsi >> new file mode 100644 >> index 0000000000..370c53800d >> --- /dev/null >> +++ b/arch/riscv/dts/fu540-sdram-ddr4.dtsi >> @@ -0,0 +1,1489 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * (C) Copyright 2020 SiFive, Inc >> + */ >> + >> +&dmc { >> + sifive,sdram-params = < > >Are these parameter values SoC specific, or board specific? If it's board >specific, it should be renamed to hifive-unleashed-a00_sdram_ddr4.dtsi, or >put it directly into hifive-unleashed-a00-u-boot.dtsi
As far as I know, it's a board specific. I will rename it to hifive-unleashed-a00_sdram_ddr4.dtsi. > >> + 0x00000a00 /* DENALI_CTL_00_DATA */ >> + 0x00000000 /* DENALI_CTL_01_DATA */ >> + 0x00000000 /* DENALI_CTL_02_DATA */ >> + 0x00000000 /* DENALI_CTL_03_DATA */ >> + 0x00000000 /* DENALI_CTL_04_DATA */ >> + 0x00000000 /* DENALI_CTL_05_DATA */ >> + 0x0000000a /* DENALI_CTL_06_DATA */ >> + 0x0002d362 /* DENALI_CTL_07_DATA */ >> + 0x00071073 /* DENALI_CTL_08_DATA */ >> + 0x0a1c0255 /* DENALI_CTL_09_DATA */ >> + 0x1c1c0400 /* DENALI_CTL_10_DATA */ > >[snip] > >Regards, >Bin
