Use the standard BIT() macro for bitfield definitions.
Signed-off-by: Dario Binacchi <dario...@libero.it>
---
drivers/video/am335x-fb.c | 16 ++++++++--------
drivers/video/am335x-fb.h | 12 ++++++------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/video/am335x-fb.c b/drivers/video/am335x-fb.c
index 51c1af587f..18e3bd1f35 100644
--- a/drivers/video/am335x-fb.c
+++ b/drivers/video/am335x-fb.c
@@ -27,11 +27,11 @@
/* LCD Control Register */
#define LCD_CLK_DIVISOR(x) ((x) << 8)
-#define LCD_RASTER_MODE 0x01
+#define LCD_RASTER_MODE BIT(0)
/* LCD Clock Enable Register */
-#define LCD_CORECLKEN (0x01 << 0)
-#define LCD_LIDDCLKEN (0x01 << 1)
-#define LCD_DMACLKEN (0x01 << 2)
+#define LCD_CORECLKEN BIT(0)
+#define LCD_LIDDCLKEN BIT(1)
+#define LCD_DMACLKEN BIT(2)
/* LCD DMA Control Register */
#define LCD_DMA_BURST_SIZE(x) ((x) << 4)
#define LCD_DMA_BURST_1 0x0
@@ -57,11 +57,11 @@
#define LCD_HFPMSB(x) ((((x)-1) & 0x300) >> 8)
#define LCD_INVMASK(x) ((x) & 0x3F00000)
/* LCD Raster Ctrl Register */
-#define LCD_TFT_24BPP_MODE (1 << 25)
-#define LCD_TFT_24BPP_UNPACK (1 << 26)
+#define LCD_TFT_24BPP_MODE BIT(25)
+#define LCD_TFT_24BPP_UNPACK BIT(26)
#define LCD_PALMODE_RAWDATA (0x02 << 20)
-#define LCD_TFT_MODE (0x01 << 7)
-#define LCD_RASTER_ENABLE (0x01 << 0)
+#define LCD_TFT_MODE BIT(7)
+#define LCD_RASTER_ENABLE BIT(0)
/* Macro definitions */
diff --git a/drivers/video/am335x-fb.h b/drivers/video/am335x-fb.h
index f5883c02dd..ad9b015e09 100644
--- a/drivers/video/am335x-fb.h
+++ b/drivers/video/am335x-fb.h
@@ -7,7 +7,7 @@
#ifndef AM335X_FB_H
#define AM335X_FB_H
-#define HSVS_CONTROL (0x01 << 25) /*
+#define HSVS_CONTROL BIT(25) /*
* 0 = lcd_lp and lcd_fp are driven on
* opposite edges of pixel clock than
* the lcd_pixel_o
@@ -17,7 +17,7 @@
* Matrix displays the edge timing is
* fixed
*/
-#define HSVS_RISEFALL (0x01 << 24) /*
+#define HSVS_RISEFALL BIT(24) /*
* 0 = lcd_lp and lcd_fp are driven on
* the rising edge of pixel clock (bit
* 25 must be set to 1)
@@ -25,19 +25,19 @@
* the falling edge of pixel clock (bit
* 25 must be set to 1)
*/
-#define DE_INVERT (0x01 << 23) /*
+#define DE_INVERT BIT(23) /*
* 0 = DE is low-active
* 1 = DE is high-active
*/
-#define PXCLK_INVERT (0x01 << 22) /*
+#define PXCLK_INVERT BIT(22) /*
* 0 = pix-clk is high-active
* 1 = pic-clk is low-active
*/
-#define HSYNC_INVERT (0x01 << 21) /*
+#define HSYNC_INVERT BIT(21) /*
* 0 = HSYNC is active high
* 1 = HSYNC is avtive low
*/
-#define VSYNC_INVERT (0x01 << 20) /*
+#define VSYNC_INVERT BIT(20) /*
* 0 = VSYNC is active high
* 1 = VSYNC is active low
*/
--
2.24.0
