Hi Marek, > From: Marek Vasut <ma...@denx.de> > Sent: mardi 28 janvier 2020 13:16 > > On 1/28/20 10:11 AM, Patrick Delaunay wrote: > > From: Antonio Borneo <antonio.bor...@st.com> > > > > LTDC modifies the clock frequency to adapt it to the display. Such > > frequency change is not detected by the FDCAN driver that instead > > cache the value at probe and pretend to use it later. > > > > Keep the LTDC alone on PLL4_Q by moving the FDCAN to PLL4_R. > > Now this looks like a grisly workaround. Can you fix the LTDC driver to do > something sane on boards which didn't update bootloader yet ?
In fact it more a issue in the initial clock-tree used when I upstream the ST board the first time... based on our delivery v1.0.0 It is already corrected in downstream on v1.1.0: + For U-Boot = https://github.com/STMicroelectronics/u-boot/commit/d62f14dece32e41c2854b9ff44aca7b8384aa8a0 + For TF-A = https://github.com/STMicroelectronics/arm-trusted-firmware/commit/9a24ceda6c3ba060d9acf2b26d069fedde9f0807 The LTDC/DSI need to set the pixel clock according the panel configuration and settings: it is normal and needed. But If the pixel clock is shared with FDCAN, which expects that its input clock is fixed, an issue occur when the pixel clock change. We could add protection in FDCAN driver (don't assume fixed clock in probe for example) but anyway that don't protect for any issue (pending FDCAN transfer when pixel clock change). The main issue is that we try to share a clock source between 2 IP that are not compatible: 1/ FDCAN => clock source configurated by CLK_FDCAN_PLL4Q 2/ pixel clocl for LTDC and DSI = LTDC_PX or DSI_PX => _PLL4_Q (hardcoded in RCC) The clock source for pixel clock PLL4_Q need only managed only by LDTC as it can modify the source clock. It is why we decide to change the reference clock tree used on ST Microelectronic boards. And unfortunately that impacts the first stage bootloader. For information in our solution the clock tree is fixed and configurated at boot by first stage bootloader (TF-A normally for trusted boot chain / SPL for basic boot chain) as this configuration is done in secured registers with information provided by device-tree. See https://wiki.st.com/stm32mpu/wiki/STM32MP15_clock_tree for details Regards Patrick
