> -----Original Message-----
> From: Marek Vasut <ma...@denx.de>
> Sent: Thursday, November 21, 2019 6:12 PM
> To: Tan, Ley Foon <ley.foon....@intel.com>; u-boot@lists.denx.de
> Cc: See, Chin Liang <chin.liang....@intel.com>; Dalon Westergreen
> <dwest...@gmail.com>; Dinh Nguyen <dingu...@kernel.org>; Simon
> Goldschmidt <simon.k.r.goldschm...@gmail.com>; Chee, Tien Fong
> <tien.fong.c...@intel.com>
> Subject: Re: [PATCH] ARM: socfpga: Unreset NAND in SPL on Gen5
>
> On 11/21/19 11:08 AM, Tan, Ley Foon wrote:
> [...]
>
> Hi,
>
> >> In case the SPL on Gen5 loads U-Boot from NAND, unreset the NAND IP
> >> explicitly in the platform code as the denali-spl driver is not aware
> >> of DM at all.
> >>
> >> Signed-off-by: Marek Vasut <ma...@denx.de>
> >> Cc: Chin Liang See <chin.liang....@intel.com>
> >> Cc: Dalon Westergreen <dwest...@gmail.com>
> >> Cc: Dinh Nguyen <dingu...@kernel.org>
> >> Cc: Ley Foon Tan <ley.foon....@intel.com>
> >> Cc: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
> >> Cc: Tien Fong Chee <tien.fong.c...@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon....@intel.com>
> >> ---
> >> arch/arm/mach-socfpga/spl_gen5.c | 7 +++++++
> >> 1 file changed, 7 insertions(+)
> >>
> >> diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-
> >> socfpga/spl_gen5.c index 47e63709ad..408e409375 100644
> >> --- a/arch/arm/mach-socfpga/spl_gen5.c
> >> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> >> @@ -138,6 +138,13 @@ void board_init_f(ulong dummy)
> >> if (ret)
> >> debug("Reset init failed: %d\n", ret);
> >>
> >> +#ifdef CONFIG_SPL_NAND_DENALI
> >> + struct socfpga_reset_manager *reset_manager_base =
> >> + (struct socfpga_reset_manager
> >> *)SOCFPGA_RSTMGR_ADDRESS;
> >> +
> >> + clrbits_le32(&reset_manager_base->per_mod_reset, BIT(4)); #endif
> >> +
> > Normal Denali Nand driver (denali_dt_probe()) is not running in SPL Gen5?
>
> Nope, I tried to put the whole MTD subsystem into SPL, but it just does not
> fit
> into the 64 kiB we have on Gen5. It does fit on A10 which has
> 256 kiB of OCRAM, but I can't easily replace the SoC here. Hence this denali-
> spl.
Okay, now I understand your problem here.
>
> > I am enabling NAND for Agilex recently, but didn't notice need to de-assert
> NAND reset outside of denali nand driver.
>
> How much OCRAM does Agilex have again ? :-)
Agilex have 256KB OCRAM as in S10.
Regards
Ley Foon
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