Dear Kumar Gala, In message <1279120502-6289-8-git-send-email-ga...@kernel.crashing.org> you wrote: > From: york <york...@freescale.com> > > If enabled in config file and hwconfig, the memory test is performed > after DDR initialization when U-boot stills runs in flash and cache. > Whole memory is testable. However, only the low 2GB space is mapped > for DDR. The testing is conducted in the 2GB window and uses TLBs to > map the higher physical address into the 2GB window if the total > memory is more than 2GB. After the testing, DDR is remapped with up > to 2GB memory from the lowest address. > > Memory testing has different patterns which may be improved later. > > If memory test fails, DDR DIMM SPD and DDR controller registers are > dumped. All zero values are omitted for better viewing. > > A worker function __setup_ddr_tlbs() is introduced to implemente more > control on physical address mapping. > > Signed-off-by: York Sun <york...@freescale.com> > --- > arch/powerpc/cpu/mpc85xx/Makefile | 2 + > arch/powerpc/cpu/mpc85xx/memtest.c | 369 > ++++++++++++++++++++++++++++++++++++
NAK. Please do not reinvent the wheel and add yet another meory test. Use one of the existing memory tests we already have - post/drivers/memory.c comes to mind. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de "A dirty mind is a joy forever." - Randy Kunkee _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
