From: Thor Thayer <thor.tha...@linux.intel.com>
Enable TCU access through the Stratix10 CCU so that the
SMMU can access the SDRAM.
Signed-off-by: Thor Thayer <thor.tha...@linux.intel.com>
---
arch/arm/mach-socfpga/include/mach/firewall_s10.h | 7 +++++++
drivers/ddr/altera/sdram_s10.c | 14 ++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h
b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
index b96f779f1487..d698e4b9e2a1 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall_s10.h
@@ -95,6 +95,13 @@ struct socfpga_firwall_l4_sys {
#define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE0 0x2c520
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1A 0x2c540
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1B 0x2c560
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1C 0x2c580
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1D 0x2c5a0
+#define CCU_TCU_MPRT_ADBASE_MEMSPACE1E 0x2c5c0
+
#define CCU_ADMASK_P_MASK BIT(0)
#define CCU_ADMASK_NS_MASK BIT(1)
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index 56cbbac9fe1f..bc027c478452 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -323,6 +323,20 @@ static int sdram_mmr_init_full(struct udevice *dev)
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
CCU_ADBASE_DI_MASK);
+ /* Enable access to DDR from TCU */
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
+ CCU_ADBASE_DI_MASK);
+ clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
+ CCU_ADBASE_DI_MASK);
+
/* this enables nonsecure access to DDR */
/* mpuregion0addr_limit */
FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
--
2.7.4
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