Enable CLK and SPL_CLK so that the new readonly clock driver is used.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
---
Changes in v2: None
arch/arm/mach-socfpga/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 9efdcd6f10..81052f27d5 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -53,7 +53,9 @@ config TARGET_SOCFPGA_CYCLONE5
config TARGET_SOCFPGA_GEN5
bool
+ select CLK
select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
imply FPGA_SOCFPGA
imply SPL_SIZE_LIMIT_SUBTRACT_GD
imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
--
2.20.1
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