> -----Original Message-----
> From: Pankaj Bansal
> Sent: 2019年10月14日 19:43
> To: Priyanka Jain <priyanka.j...@nxp.com>; Xiaowei Bao
> <xiaowei....@nxp.com>; Tom Rini <tr...@konsulko.com>; Z.q. Hou
> <zhiqiang....@nxp.com>
> Cc: u-boot@lists.denx.de; Pankaj Bansal <pankaj.ban...@nxp.com>
> Subject: [PATCH] pci: layerscape: Only set EP CFG READY bit
>
> As part of EP setup, we want to set the config ready bit of controller, so
> that
> RC can read the config space of EP.
> Now, when we set the config ready bit we are inadvertently clearing the
> LTSSM_EN bit in same register, which restarts the link tarining between RC
> and EP.
> Therefore, just set the desired CFG_READY bit (bit 0), while leaving the other
> bits unchanged.
>
> Signed-off-by: Pankaj Bansal <pankaj.ban...@nxp.com>
> ---
> drivers/pci/pcie_layerscape.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index d8a7b7c865..bb2ec7c2ce 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -407,7 +407,11 @@ static void ls_pcie_ep_setup_bars(void *bar_base)
>
> static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) {
> - ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG);
> + u32 config;
> +
> + config = ctrl_readl(pcie, PCIE_PF_CONFIG);
> + config |= PCIE_CONFIG_READY;
> + ctrl_writel(pcie, config, PCIE_PF_CONFIG);
> }
>
> static void ls_pcie_setup_ep(struct ls_pcie *pcie)
> --
> 2.17.1
Reviewed-by: Hou Zhiqiang <zhiqiang....@nxp.com>
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