Hi Fabio,
get a lost patch, I pick it up:
On 18/07/19 20:04, Fabio Estevam wrote:
> Place imx_ddr_size() into a separate file.
>
> The motivation for doing this is to be able to easily reuse
> imx_ddr_size() on i.MX7ULP.
>
> Currently imx_ddr_size() is inside arch/arm/mach-imx/cpu.c, which
> is not built for i.MX7ULP.
>
> Changing the logic to allow building cpu.c for i.MX7UP would
> require adding several ifdef's, leading to a not a very elegant
> solution.
>
> To allow better reuse, just place imx_ddr_size() into a common
> mmdc_size.c file.
>
> Signed-off-by: Fabio Estevam <feste...@gmail.com>
> ---
> arch/arm/mach-imx/Makefile | 2 +-
> arch/arm/mach-imx/cpu.c | 53 ---------------------------------
> arch/arm/mach-imx/mmdc_size.c | 55 +++++++++++++++++++++++++++++++++++
> 3 files changed, 56 insertions(+), 54 deletions(-)
> create mode 100644 arch/arm/mach-imx/mmdc_size.c
>
> diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
> index 898478fc4a..0c8519be94 100644
> --- a/arch/arm/mach-imx/Makefile
> +++ b/arch/arm/mach-imx/Makefile
> @@ -20,7 +20,7 @@ obj-y += cpu.o
> endif
>
> ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
> -obj-y += cpu.o speed.o
> +obj-y += cpu.o speed.o mmdc_size.o
This does not filter MX51, code is not common for it. What do you mind
if I pick it up with :
ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
obj-y += cpu.o speed.o
ifneq ($(CONFIG_MX51),y)
obj-y += mmdc_size.o
endif
Regards,
Stefano
> obj-$(CONFIG_GPT_TIMER) += timer.o
> obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
> endif
> diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
> index 3a8cf30c06..0b30ff40cd 100644
> --- a/arch/arm/mach-imx/cpu.c
> +++ b/arch/arm/mach-imx/cpu.c
> @@ -87,59 +87,6 @@ static char *get_reset_cause(void)
> }
> #endif
>
> -#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
> -#if defined(CONFIG_MX53)
> -#define MEMCTL_BASE ESDCTL_BASE_ADDR
> -#else
> -#define MEMCTL_BASE MMDC_P0_BASE_ADDR
> -#endif
> -static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
> -static const unsigned char bank_lookup[] = {3, 2};
> -
> -/* these MMDC registers are common to the IMX53 and IMX6 */
> -struct esd_mmdc_regs {
> - uint32_t ctl;
> - uint32_t pdc;
> - uint32_t otc;
> - uint32_t cfg0;
> - uint32_t cfg1;
> - uint32_t cfg2;
> - uint32_t misc;
> -};
> -
> -#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
> -#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
> -#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
> -#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
> -#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
> -
> -/*
> - * imx_ddr_size - return size in bytes of DRAM according MMDC config
> - * The MMDC MDCTL register holds the number of bits for row, col, and data
> - * width and the MMDC MDMISC register holds the number of banks. Combine
> - * all these bits to determine the meme size the MMDC has been configured for
> - */
> -unsigned imx_ddr_size(void)
> -{
> - struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
> - unsigned ctl = readl(&mem->ctl);
> - unsigned misc = readl(&mem->misc);
> - int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
> -
> - bits += ESD_MMDC_CTL_GET_ROW(ctl);
> - bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
> - bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
> - bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
> - bits += ESD_MMDC_CTL_GET_CS1(ctl);
> -
> - /* The MX6 can do only 3840 MiB of DRAM */
> - if (bits == 32)
> - return 0xf0000000;
> -
> - return 1 << bits;
> -}
> -#endif
> -
> #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
>
> const char *get_imx_type(u32 imxtype)
> diff --git a/arch/arm/mach-imx/mmdc_size.c b/arch/arm/mach-imx/mmdc_size.c
> new file mode 100644
> index 0000000000..8a3c6bdea6
> --- /dev/null
> +++ b/arch/arm/mach-imx/mmdc_size.c
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +
> +#include <common.h>
> +#include <asm/io.h>
> +
> +#if defined(CONFIG_MX53)
> +#define MEMCTL_BASE ESDCTL_BASE_ADDR
> +#else
> +#define MEMCTL_BASE MMDC_P0_BASE_ADDR
> +#endif
> +static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
> +static const unsigned char bank_lookup[] = {3, 2};
> +
> +/* these MMDC registers are common to the IMX53 and IMX6 */
> +struct esd_mmdc_regs {
> + uint32_t ctl;
> + uint32_t pdc;
> + uint32_t otc;
> + uint32_t cfg0;
> + uint32_t cfg1;
> + uint32_t cfg2;
> + uint32_t misc;
> +};
> +
> +#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
> +#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
> +#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
> +#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
> +#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
> +
> +/*
> + * imx_ddr_size - return size in bytes of DRAM according MMDC config
> + * The MMDC MDCTL register holds the number of bits for row, col, and data
> + * width and the MMDC MDMISC register holds the number of banks. Combine
> + * all these bits to determine the meme size the MMDC has been configured for
> + */
> +unsigned imx_ddr_size(void)
> +{
> + struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
> + unsigned ctl = readl(&mem->ctl);
> + unsigned misc = readl(&mem->misc);
> + int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
> +
> + bits += ESD_MMDC_CTL_GET_ROW(ctl);
> + bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
> + bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
> + bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
> + bits += ESD_MMDC_CTL_GET_CS1(ctl);
> +
> + /* The MX6 can do only 3840 MiB of DRAM */
> + if (bits == 32)
> + return 0xf0000000;
> +
> + return 1 << bits;
> +}
>
--
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