Hi Simon,
On Wed, Sep 25, 2019 at 10:59 PM Simon Glass <s...@chromium.org> wrote:
>
> At present we don't support loading microcode with FSP2. The correct way
> to do this is by adding it to the FIT. For now, disable including
> microcode in the image.
>
> Signed-off-by: Simon Glass <s...@chromium.org>
> ---
>
> arch/x86/Kconfig | 4 ++++
> arch/x86/dts/u-boot.dtsi | 11 +++++++++++
> 2 files changed, 15 insertions(+)
>
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index e797612e30e..fce3c1d92a3 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -580,6 +580,10 @@ config HAVE_REFCODE
> broadwell) U-Boot will be missing some critical setup steps.
> Various peripherals may fail to work.
>
> +config HAVE_MICROCODE
> + bool
> + default y if !FSP_VERSION2
> +
> config SMP
> bool "Enable Symmetric Multiprocessing"
> default n
> diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
> index 049f47c9ffd..35129d0510b 100644
> --- a/arch/x86/dts/u-boot.dtsi
> +++ b/arch/x86/dts/u-boot.dtsi
> @@ -37,9 +37,15 @@
> };
> #endif
> #ifdef CONFIG_TPL
> +#ifdef CONFIG_HAVE_MICROCODE
> u-boot-tpl-with-ucode-ptr {
> offset = <CONFIG_TPL_TEXT_BASE>;
> };
> +#else
> + u-boot-tpl {
> + offset = <0xffff0000>;
Why hardcode?
> + };
> +#endif
> u-boot-tpl-dtb {
> };
> u-boot-spl {
> @@ -77,11 +83,16 @@
> offset = <CONFIG_SYS_TEXT_BASE>;
> };
> #endif
> +#ifdef CONFIG_HAVE_MICROCODE
> u-boot-dtb-with-ucode {
> };
> u-boot-ucode {
> align = <16>;
> };
> +#else
> + u-boot-dtb {
> + };
> +#endif
> #ifdef CONFIG_X86_HAS_FIT
> intel-fit {
> };
> --
Regards,
Bin
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