On Tue, 2019-09-17 at 10:57 +0800, Kever Yang wrote: > Hi Kurt, > > Could you try with below update: > > > diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi > b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi > index 4a4414a960..dc9db047cb 100644 > --- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi > +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi > @@ -13,8 +13,8 @@ > 0x2 > 0x1 > 0x0 > - 0xf > - 0xf > + 0x10 > + 0x10 > 1 > 0x80241d22 > 0x15050f08 > @@ -28,8 +28,8 @@ > 0x2 > 0x1 > 0x0 > - 0xf > - 0xf > + 0x10 > + 0x10 > 1 > 0x80241d22 > 0x15050f08 > > Thanks, > - Kever
Hi Kever, Yes, that diff does correct the memory size detection for my board: U-Boot TPL 2019.10-rc3-00332-ga314ec1bfd-dirty (Sep 17 2019 - 11:55:26) con reg cru , cic , grf , sgrf , pmucru , pmu Starting SDRAM initialization... sdram_init: data trained for rank 1, ch 0 sdram_init: data trained for rank 1, ch 1 Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB 256B stride lpddr4_set_ctl: channel 0 training pass lpddr4_set_ctl: channel 1 training pass lpddr4_set_rate: change freq to 400 mhz 0, 1 lpddr4_set_ctl: channel 0 training pass lpddr4_set_ctl: channel 1 training pass lpddr4_set_rate: change freq to 800 mhz 1, 0 Finish SDRAM initialization... Trying to boot from BOOTROM Returning to boot ROM... Thank you, -Kurt _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
