Hi Prabhakar, On Mon, Aug 26, 2019 at 9:00 PM Bin Meng <bmeng...@gmail.com> wrote: > > Hi Prabhakar, > > On Mon, Aug 26, 2019 at 5:10 PM Prabhakar Kushwaha > <prabhakar.kushw...@nxp.com> wrote: > > > > Dear Bin, > > > > > -----Original Message----- > > > From: Bin Meng <bmeng...@gmail.com> > > > Sent: Monday, August 26, 2019 2:21 PM > > > To: Z.q. Hou <zhiqiang....@nxp.com> > > > Cc: u-boot@lists.denx.de; Prabhakar Kushwaha > > > <prabhakar.kushw...@nxp.com> > > > Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 erratum > > > A003 > > > > > > Hi Zhiqiang, > > > > > > On Mon, Aug 26, 2019 at 4:34 PM Z.q. Hou <zhiqiang....@nxp.com> wrote: > > > > > > > > Hi Bin, > > > > > > > > Thanks a lot for your comments! > > > > > > > > > -----Original Message----- > > > > > From: Bin Meng <bmeng...@gmail.com> > > > > > Sent: 2019年8月26日 13:59 > > > > > To: Z.q. Hou <zhiqiang....@nxp.com> > > > > > Cc: u-boot@lists.denx.de; Prabhakar Kushwaha > > > > > <prabhakar.kushw...@nxp.com> > > > > > Subject: Re: [PATCHv2 1/3] dm: pcie_fsl: Fix workaround of P4080 > > > > > erratum > > > > > A003 > > > > > > > > > > Hi Zhiqiang, > > > > > > > > > > On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou <zhiqiang....@nxp.com> > > > > > wrote: > > > > > > > > > > > > From: Hou Zhiqiang <zhiqiang....@nxp.com> > > > > > > > > > > > > In the workaround of P4080 erratum A003, it uses the macro > > > > > > CONFIG_SYS_FSL_CORENET_SERDES_ADDR to get the SerDes block > > > > > register > > > > > > address, the CONFIG_SYS_FSL_CORENET_SERDES_ADDR is defined as > > > > > > following: > > > > > > > > > > > > (CONFIG_SYS_IMMR + > > > > > CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) > > > > > > > > > > > > The problem is the macro CONFIG_SYS_FSL_CORENET_SERDES_ADDR is > > > > > defined > > > > > > on both corenet and non-corenet platforms (though it should be > > > > > > defined only on corenet platforms), but the macro > > > > > > CONFIG_SYS_FSL_CORENET_SERDES_OFFSET is only defined on corenet > > > > > > platforms, so when enabled this driver on non-corenet platforms, > > > > > > > > > > so when enabling > > > > > > > > The following series will enable DM PCIe on some PowerPC platforms > > > > including MPC8548CDS, which isn't a CORENET platform. > > > > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fpatch > > > > > > > work.ozlabs.org%2Fproject%2Fuboot%2Flist%2F%3Fseries%3D120966&dat > > > a > > > > > > > =02%7C01%7Cprabhakar.kushwaha%40nxp.com%7C927d704c60734c63fb7708 > > > d72a02 > > > > > > > 7cd0%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63702406248371 > > > 8776&a > > > > > > > mp;sdata=HLHA1%2FXmSxPPz%2FOF%2BWu30kQDD0xGsWOhxyHBEuMs8hw% > > > 3D&rese > > > > rved=0 > > > > > > Is this patch series merged? Or still in the review queue. I would like > > > to have a > > > look. > > > > > > > This patch series has not been merged. I am in process of integrating it. > > > > powerpc: Enable PCIe DM drvier for some platforms: > > http://patchwork.ozlabs.org/project/uboot/list/?series=120966 > > > > If you have feedback. Please do share. > > > > I can wait to send in in rc4 or rc5. > > Thanks for letting me know the patch status. I will take a look soon. >
Thanks to Zhiqiang's quick response to my review comments, now I have finished the review for patch series http://patchwork.ozlabs.org/project/uboot/list/?series=120966. Regards, Bin _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
