Re: [U-Boot] [PATCHv2 2/3] dm: pcie_fsl: Fix the Class Code fixup function

[Z.q. Hou]

Hi Bin,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bin Meng <bmeng...@gmail.com>
> Sent: 2019年8月26日 14:07
> To: Z.q. Hou <zhiqiang....@nxp.com>
> Cc: u-boot@lists.denx.de; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>
> Subject: Re: [PATCHv2 2/3] dm: pcie_fsl: Fix the Class Code fixup function
> 
> Hi Zhiqiang,
> 
> On Sun, Aug 25, 2019 at 11:42 PM Z.q. Hou <zhiqiang....@nxp.com> wrote:
> >
> > From: Hou Zhiqiang <zhiqiang....@nxp.com>
> >
> > The Class Code fixup method was changed from PCIe block revision 3.0,
> > the current fixup is only valid for the revision 3.0 and the later
> > ones.
> >
> > This patch is to add the Class Code fixup for the block revision <
> > 3.0.
> >
> > Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
> > ---
> > V2:
> >  - No change.
> >
> >  drivers/pci/pcie_fsl.c | 17 +++++++++++++----  drivers/pci/pcie_fsl.h
> > |  3 +++
> >  2 files changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index
> > 29b50f2376..60d274124b 100644
> > --- a/drivers/pci/pcie_fsl.c
> > +++ b/drivers/pci/pcie_fsl.c
> > @@ -502,12 +502,21 @@ static int fsl_pcie_fixup_classcode(struct
> fsl_pcie *pcie)
> >         ccsr_fsl_pci_t *regs = pcie->regs;
> >         u32 val;
> >
> > -       setbits_be32(&regs->dbi_ro_wr_en, 0x01);
> > -       fsl_pcie_hose_read_config_dword(pcie, PCI_CLASS_REVISION,
> &val);
> > +       if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
> > +               setbits_be32(&regs->dbi_ro_wr_en, 0x01);
> > +               fsl_pcie_hose_read_config_dword(pcie,
> PCI_CLASS_REVISION, &val);
> > +               val &= 0xff;
> > +               val |= PCI_CLASS_BRIDGE_PCI << 16;
> > +               fsl_pcie_hose_write_config_dword(pcie,
> PCI_CLASS_REVISION, val);
> > +               clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
> > +
> > +               return 0;
> > +       }
> > +
> 
> I think you can use a variable "int class_rev_reg", then
> 
> if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
>     class_rev_reg = PCI_CLASS_REVISION;
>     setbits_be32(&regs->dbi_ro_wr_en, 0x01); } else {
>     class_rev_reg = CSR_CLASSCODE;
> }
> 
> then do the same for both <= 3.0 IP and > 3.0 IP,
> 
> and finally
> 
> if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
>     clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
> 

Good idea! Will rewrite this func in v3.

Thanks,
Zhiqiang

> > +       fsl_pcie_hose_read_config_dword(pcie, CSR_CLASSCODE, &val);
> >         val &= 0xff;
> >         val |= PCI_CLASS_BRIDGE_PCI << 16;
> > -       fsl_pcie_hose_write_config_dword(pcie, PCI_CLASS_REVISION,
> val);
> > -       clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
> > +       fsl_pcie_hose_write_config_dword(pcie, CSR_CLASSCODE, val);
> >
> >         return 0;
> >  }
> > diff --git a/drivers/pci/pcie_fsl.h b/drivers/pci/pcie_fsl.h index
> > 35a740241e..cdf28dbea2 100644
> > --- a/drivers/pci/pcie_fsl.h
> > +++ b/drivers/pci/pcie_fsl.h
> > @@ -9,6 +9,9 @@
> >  #ifndef _PCIE_FSL_H_
> >  #define _PCIE_FSL_H_
> >
> > +/* GPEX CSR */
> > +#define CSR_CLASSCODE                  0x474
> > +
> >  #ifdef CONFIG_SYS_FSL_PCI_VER_3_X
> >  #define FSL_PCIE_CAP_ID                        0x70
> >  #else
> > --
> 
> Regards,
> Bin
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