> Sent: Monday, August 19, 2019 2:25 PM
> To: Troy Kisky <troy.ki...@boundarydevices.com>; Fabio Estevam
> <fabio.este...@nxp.com>; Stefano Babic <sba...@denx.de>;
> u-boot@lists.denx.de; Jacky Bai <ping....@nxp.com>
> Subject: RE: imx: add i.MX8MQ EVK support
>
> Loop Jacky who has more knowledge in the ddr stuff.
>
> > Subject: re: imx: add i.MX8MQ EVK support
> >
> > Hi Peng
> >
> > In spl.c you have
> >
> > _________
> > static void spl_dram_init(void)
> > {
> > /* ddr init */
> > if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
> > ddr_init(&dram_timing);
> > else
> > ddr_init(&dram_timing_b0);
> > }
> >
> > _________
> >
> > Could you explain why this is dependent on chip rev ?
It is due an errata in DDR PHY, for chip Rev lower than 2.1, set point < 667mts
can NOT be supported
> >
> > It it just the extra frequency in lpddr4_timing.c ?
> >
> > __________
> > {
> > /* P1 100mts 1D */
> > .drate = 100,
> > .fw_type = FW_1D_IMAGE,
> > .fsp_cfg = lpddr4_fsp2_cfg,
> > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
> > },
> > _________
> >
> >
> > Will other i.MX8MQ boards also need this check ?
> >
For most of the customer board, I think the chip Rev is 2.1, so no need such
check.
> >
> > Thanks
> > Troy
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