Hi Peng In spl.c you have
_________ static void spl_dram_init(void) { /* ddr init */ if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) ddr_init(&dram_timing); else ddr_init(&dram_timing_b0); } _________ Could you explain why this is dependent on chip rev ? It it just the extra frequency in lpddr4_timing.c ? __________ { /* P1 100mts 1D */ .drate = 100, .fw_type = FW_1D_IMAGE, .fsp_cfg = lpddr4_fsp2_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), }, _________ Will other i.MX8MQ boards also need this check ? Thanks Troy _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot