> Subject: Re: [PATCH 20/22] arm: dts: import i.MX8MM dtsi
>
> On 09.08.19 06:15, Peng Fan wrote:
> > Import i.MX8MM dtsi from Linux Kernel, commit <0a8ad0ffa4d8> ("Merge
> > tag 'for-linus-5.3-ofs1' of
> > git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
> >
> > Signed-off-by: Peng Fan <peng....@nxp.com>
> > ---
> > arch/arm/dts/imx8mm.dtsi | 733
> +++++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 733 insertions(+)
> > create mode 100644 arch/arm/dts/imx8mm.dtsi
> >
> > diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi new
> > file mode 100644 index 0000000000..6b407a94c0
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8mm.dtsi
> [...]
> > +
> > + usdhc1: mmc@30b40000 {
> > + compatible = "fsl,imx8mm-usdhc",
> > "fsl,imx7d-usdhc";
> > + reg = <0x30b40000 0x10000>;
> > + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > + <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
> > + <&clk IMX8MM_CLK_USDHC1_ROOT>;
> > + clock-names = "ipg", "ahb", "per";
> > + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
> > + assigned-clock-rates = <400000000>;
> > + fsl,tuning-start-tap = <20>;
> > + fsl,tuning-step= <2>;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + usdhc2: mmc@30b50000 {
> > + compatible = "fsl,imx8mm-usdhc",
> > "fsl,imx7d-usdhc";
> > + reg = <0x30b50000 0x10000>;
> > + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > + <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
> > + <&clk IMX8MM_CLK_USDHC2_ROOT>;
> > + clock-names = "ipg", "ahb", "per";
>
> I know this has been copied from Linux, but I wonder why the
> 'assigned-clocks' and 'assigned-clock-rates' are missing here, while they
> exist
> for usdhc1 and usdhc3.
The upstream Linux dts does not have it. It might be missed to be added in
Linux dts.
Regards,
Peng.
>
> The SD-card connected to usdhc2 on my board works without it, though.
>
> > + fsl,tuning-start-tap = <20>;
> > + fsl,tuning-step= <2>;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + usdhc3: mmc@30b60000 {
> > + compatible = "fsl,imx8mm-usdhc",
> > "fsl,imx7d-usdhc";
> > + reg = <0x30b60000 0x10000>;
> > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MM_CLK_DUMMY>,
> > + <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
> > + <&clk IMX8MM_CLK_USDHC3_ROOT>;
> > + clock-names = "ipg", "ahb", "per";
> > + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
> > + assigned-clock-rates = <400000000>;
> > + fsl,tuning-start-tap = <20>;
> > + fsl,tuning-step= <2>;
> > + bus-width = <4>;
> > + status = "disabled";
> > + };
> [...]
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