On 5/17/19 3:08 PM, Christophe Roullier wrote:
> Called to configure Ethernet PHY interface selection and
> configure clock selection in RCC Ethernet clock tree.
>
> Signed-off-by: Christophe Roullier <christophe.roull...@st.com>
> ---
>
> Changes in v2: None
>
> board/st/stm32mp1/stm32mp1.c | 68 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 3 deletions(-)
>
> diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c
> index 76917b022ed..e120fc57223 100644
> --- a/board/st/stm32mp1/stm32mp1.c
> +++ b/board/st/stm32mp1/stm32mp1.c
> @@ -51,9 +51,9 @@
> #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
>
> #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
> -#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21)
> -#define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21)
> -#define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21)
> +#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
> +#define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
> +#define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
>
> /*
> * Get a global data pointer
> @@ -504,3 +504,65 @@ void board_quiesce_devices(void)
> {
> setup_led(LEDST_OFF);
> }
> +
> +/* board interface eth init */
> +/* this is a weak define that we are overriding */
> +int board_interface_eth_init(phy_interface_t interface_type,
> + bool eth_clk_sel_reg, bool eth_ref_clk_sel_reg)
> +{
> + u8 *syscfg;
> + u32 value;
> +
> + syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
> +
> + if (!syscfg)
> + return -ENODEV;
> +
> + switch (interface_type) {
> + case PHY_INTERFACE_MODE_MII:
> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
> + debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
> + break;
> + case PHY_INTERFACE_MODE_GMII:
> + if (eth_clk_sel_reg)
> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
> + SYSCFG_PMCSETR_ETH_CLK_SEL;
> + else
> + value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
> + debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + if (eth_ref_clk_sel_reg)
> + value = SYSCFG_PMCSETR_ETH_SEL_RMII |
> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
> + else
> + value = SYSCFG_PMCSETR_ETH_SEL_RMII;
> + debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
> + break;
> + case PHY_INTERFACE_MODE_RGMII:
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + if (eth_clk_sel_reg)
> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
> + SYSCFG_PMCSETR_ETH_CLK_SEL;
> + else
> + value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
> + debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
> + break;
> + default:
> + debug("%s: Do not manage %d interface\n",
> + __func__, interface_type);
> + /* Do not manage others interfaces */
> + return -EINVAL;
> + }
> +
> + /* clear and set ETH configuration bits */
> + writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
> + SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
> + syscfg + SYSCFG_PMCCLRR);
> + writel(value, syscfg + SYSCFG_PMCSETR);
> +
> + return 0;
> +}
>
Applied
Thanks
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