Hi Matwey, Please add commit message for the patch.
On 05/08/2019 02:34 PM, Matwey V. Kornilov wrote: > Signed-off-by: Matwey V. Kornilov <matwey.korni...@gmail.com> > --- > configs/rock64-rk3328_defconfig | 91 > +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 91 insertions(+) > create mode 100644 configs/rock64-rk3328_defconfig > > diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig > new file mode 100644 > index 0000000000..b278315035 > --- /dev/null > +++ b/configs/rock64-rk3328_defconfig > @@ -0,0 +1,91 @@ > +CONFIG_SMBIOS_MANUFACTURER="pine64" > +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" > +CONFIG_ARM=y > +CONFIG_ARCH_ROCKCHIP=y > +CONFIG_SPL_LIBCOMMON_SUPPORT=y > +CONFIG_SPL_LIBGENERIC_SUPPORT=y > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_SYS_TEXT_BASE=0x00200000 > +CONFIG_ROCKCHIP_RK3328=y > +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0 Does this SPL_REVERVE_IRAM=0 fine with support ATF? SPL TEXT_BASE is 0, and ATF starts at 0x100000, I use to reserve big enough space for ATF and U-Boot before SPL enable the relocate feature, or else it's very easy to get panic in SPL. Thanks, - Kever > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > +CONFIG_SPL_STACK_R_ADDR=0x600000 > +CONFIG_DEBUG_UART_BASE=0xFF130000 > +CONFIG_DEBUG_UART_CLOCK=24000000 > +CONFIG_DEBUG_UART=y > +CONFIG_NR_DRAM_BANKS=1 > +# CONFIG_ANDROID_BOOT_IMAGE is not set > +CONFIG_FIT=y > +CONFIG_FIT_VERBOSE=y > +CONFIG_SPL_LOAD_FIT=y > +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" > +# CONFIG_DISPLAY_CPUINFO is not set > +CONFIG_DISPLAY_BOARDINFO_LATE=y > +CONFIG_SPL_STACK_R=y > +CONFIG_SPL_ATF=y > +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y > +CONFIG_FASTBOOT_BUF_ADDR=0x800800 > +CONFIG_FASTBOOT_FLASH=y > +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 > +CONFIG_CMD_BOOTZ=y > +CONFIG_CMD_GPT=y > +CONFIG_CMD_MMC=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_USB=y > +# CONFIG_CMD_SETEXPR is not set > +CONFIG_CMD_TIME=y > +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" > +CONFIG_SPL_OF_CONTROL=y > +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names > interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" > +CONFIG_ENV_IS_IN_MMC=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_REGMAP=y > +CONFIG_SPL_REGMAP=y > +CONFIG_SYSCON=y > +CONFIG_SPL_SYSCON=y > +CONFIG_CLK=y > +CONFIG_SPL_CLK=y > +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y > +CONFIG_ROCKCHIP_GPIO=y > +CONFIG_SYS_I2C_ROCKCHIP=y > +CONFIG_MMC_DW=y > +CONFIG_MMC_DW_ROCKCHIP=y > +CONFIG_SPI_FLASH=y > +CONFIG_SF_DEFAULT_SPEED=20000000 > +CONFIG_DM_ETH=y > +CONFIG_ETH_DESIGNWARE=y > +CONFIG_GMAC_ROCKCHIP=y > +CONFIG_PHY=y > +CONFIG_PINCTRL=y > +CONFIG_SPL_PINCTRL=y > +CONFIG_PINCTRL_ROCKCHIP_RK3328=y > +CONFIG_DM_PMIC=y > +CONFIG_PMIC_RK8XX=y > +CONFIG_REGULATOR_PWM=y > +CONFIG_DM_REGULATOR_FIXED=y > +CONFIG_REGULATOR_RK8XX=y > +CONFIG_PWM_ROCKCHIP=y > +CONFIG_RAM=y > +CONFIG_SPL_RAM=y > +CONFIG_DM_RESET=y > +CONFIG_BAUDRATE=1500000 > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYSRESET=y > +CONFIG_USB=y > +CONFIG_USB_XHCI_HCD=y > +CONFIG_USB_XHCI_DWC3=y > +CONFIG_USB_EHCI_HCD=y > +CONFIG_USB_EHCI_GENERIC=y > +CONFIG_USB_OHCI_HCD=y > +CONFIG_USB_OHCI_GENERIC=y > +CONFIG_USB_DWC2=y > +CONFIG_USB_DWC3=y > +CONFIG_USB_GADGET=y > +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" > +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 > +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a > +CONFIG_USB_GADGET_DWC2_OTG=y > +CONFIG_USE_TINY_PRINTF=y > +CONFIG_SPL_TINY_MEMSET=y > +CONFIG_ERRNO_STR=y _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
