Hi George,
On 05.05.2010 23:09, George G. Davis wrote:
> The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0"
> instruction which means "Invalidate Both Caches
... Also flushes the branch target cache"
> " when in fact the intent
> is to "Clean and Invalidate Entire Data Cache".
Why don't we have to invalidate/flush the I- and BT-Cache here? I.e.
why is it sufficient to clean & invalidate the D-Cache here, only, and
remove the existing I- and BT-Cache invalidation/flushing?
What's about just adding an additional clean of the data cache before
the 'invalidate all':
+ asm ("mcr p15, 0, %0, c7, c10, 0": :"r" (i)); /* clean entire data
cache */
asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i)); /* invalidate both
caches and flush btb */
asm ("mcr p15, 0, %0, c7, c10, 4": :"r" (i)); /* mem barrier to sync
things */
?
Thanks for finding this and best regards
Dirk
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