Hi Tom, On Tue, Jun 01, 2010 at 09:38:56AM -0500, Tom Rix wrote: > gda...@mvista.com wrote: > >From: George G. Davis <gda...@mvista.com> > > > >The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" > >instruction which means "Invalidate Both Caches" when in fact the intent > >is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, > >c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate > >Both Caches" instruction to insure that memory is consistent with any > >dirty cache lines. > > > >Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so > >that they correctly describe the actual ARM1136 CP15 C7 Cache Operations > >used. > > > >Signed-off-by: George G. Davis <gda...@mvista.com> > Applied to arm/master
Er, woops, Dirk's Acked-by was not included. I reckon I should have resumitted with that included but to late now. Thanks! -- Regards, George > Thanks > Tom _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
