Hi Philippe and Andre' On Mon, Mar 18, 2019 at 10:48 AM Shyam Saini <shyam.sa...@amarulasolutions.com> wrote: > > From: Michael Trimarchi <mich...@amarulasolutions.com> > > While the exact problem is not known, based on discussion between > Philipp Tomsich and André Przywara it is guessed that exit self-refresh > timing is not set with correct value. There may be implicit enter or > exit Self-Refresh anywhere as part of some training phase. > > In ZynqMP register guide [1], which is close to the various > Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL > tXS is bits [6:0]: Self refresh exit delay. So it could be safely > increased and it only affects the time after the self-refresh “exit”, > which happens only after (re-)initialisation. > > There was no document for cpu in question so based on oscilloscope > readings [2][3] and observed result by comparing allwinner architecture. > So set it same as Allwinner H5 silicon. > > Before this patch, failure rate of was 7%. > > This was tested on A33 allwinner cpu, dual rank connection connected > with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3 > 1.5V >
Are you happy with this description? Michael > [1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html > [2] https://ibb.co/R70zmyS > [3] https://ibb.co/HVVCGQ8 > > Signed-off-by: Michael Trimarchi <mich...@amarulasolutions.com> > Signed-off-by: Shyam Saini <shyam.sa...@amarulasolutions.com> > --- > Changelogs: > V1->V2: adjust commit message > V2->V3: Adjust commit message based on V2 Discussion > --- > arch/arm/mach-sunxi/dram_sun8i_a33.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm/mach-sunxi/dram_sun8i_a33.c > b/arch/arm/mach-sunxi/dram_sun8i_a33.c > index 1da2727f9874..5da01922bfaf 100644 > --- a/arch/arm/mach-sunxi/dram_sun8i_a33.c > +++ b/arch/arm/mach-sunxi/dram_sun8i_a33.c > @@ -152,7 +152,7 @@ static void auto_set_timing_para(struct dram_para *para) > reg_val &= ~(0xff << 8); > reg_val &= ~(0xff << 0); > reg_val |= (0x33 << 8); > - reg_val |= (0x8 << 0); > + reg_val |= (0x10 << 0); > writel(reg_val, &mctl_ctl->dramtmg8); > /* Set phy interface time */ > reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) > -- > 2.11.0 > -- | Michael Nazzareno Trimarchi Amarula Solutions BV | | COO - Founder Cruquiuskade 47 | | +31(0)851119172 Amsterdam 1018 AM NL | | [`as] http://www.amarulasolutions.com | _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
