Hi Michael, On Mon, Mar 25, 2019 at 1:38 PM Michael Nazzareno Trimarchi <mich...@amarulasolutions.com> wrote:
> + /* Perform DDR DRAM calibration */ > + udelay(100); > + mmdc_do_write_level_calibration(&ddr_sysinfo); > + mmdc_do_dqs_calibration(&ddr_sysinfo); Thanks for the suggestion, but this is i.MX6 specific. i.MX7 has a different DDR controller IP and such functions do not exist there. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
