Re: [U-Boot] [PATCH V3] ddr: socfpga: Fix EMIF clear timeout

[Simon Goldschmidt]

On 09.03.2019 22:12, Marek Vasut wrote:

The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.

This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.

Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chin Liang See <chin.liang....@intel.com>
Cc: Dinh Nguyen <dingu...@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
Cc: Tien Fong Chee <tien.fong.c...@intel.com>

Reviewed-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>

---
V2: Subject should read ddr: socfpga: , fix this
V3: Zap DDR_MAX_TRIES
---
  drivers/ddr/altera/sdram_arria10.c | 25 +++++++++++--------------
  1 file changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/ddr/altera/sdram_arria10.c 
b/drivers/ddr/altera/sdram_arria10.c
index be5ce778e8..b450a1b1be 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -31,7 +31,6 @@ static u64 sdram_size_calc(void);
  #define DDR_REG_CORE2SEQ        0xFFD05078
  #define DDR_READ_LATENCY_DELAY        40
  #define DDR_SIZE_2GB_HEX      0x80000000
-#define DDR_MAX_TRIES          0x00100000

#define IO48_MMR_DRAMSTS 0xFFCFA0EC

  #define IO48_MMR_NIOS2_RESERVE0       0xFFCFA110
@@ -133,22 +132,16 @@ static unsigned char ddr_wait_bit(u32 ereg, u32 bit,

static int emif_clear(void)

  {
-       u32 i = DDR_MAX_TRIES;
-       u8 ret = 0;
-
        writel(0, DDR_REG_CORE2SEQ);

- do {

-               ret = !wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
-                                  SEQ2CORE_MASK, 1, 50, 0);
-       } while (ret && (--i > 0));
-
-       return !i;
+       return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
+                               SEQ2CORE_MASK, 0, 1000, 0);
  }

static int emif_reset(void)

  {
        u32 c2s, s2c;
+       int ret;

c2s = readl(DDR_REG_CORE2SEQ);

        s2c = readl(DDR_REG_SEQ2CORE);
@@ -159,9 +152,12 @@ static int emif_reset(void)
             readl(IO48_MMR_NIOS2_RESERVE2),
             readl(IO48_MMR_DRAMSTS));

- if ((s2c & SEQ2CORE_MASK) && emif_clear()) {

-               debug("failed emif_clear()\n");
-               return -EPERM;
+       if (s2c & SEQ2CORE_MASK) {
+               ret = emif_clear();
+               if (ret) {
+                       debug("failed emif_clear()\n");
+                       return -EPERM;
+               }
        }

writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);

@@ -173,7 +169,8 @@ static int emif_reset(void)
                debug("emif_reset interrupt acknowledged\n");
        }

- if (emif_clear()) {

+       ret = emif_clear();
+       if (ret) {
                debug("emif_clear() failed\n");
                return -EPERM;
        }

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