> > Hi, Hi Michal, > > first of all I would rephrase subject a little bit. > > Something like: > "ARM: zynq: Add missing i2c get_rate for fixing i2c SPL" OK.
> > On 14. 02. 19 6:50, Hannes Schmelzer wrote: > > The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C > > support because requesting the clock for the I2C ip-block isn't > > supported during SPL. > > > > To fixup this we add support requesting clocks for: > > - i2c0 > > - i2c1 > > > > Signed-off-by: Hannes Schmelzer <hannes.schmel...@br-automation.com> > > > > --- > > > > drivers/clk/clk_zynq.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c > > index 482f093..9a4e949 100644 > > --- a/drivers/clk/clk_zynq.c > > +++ b/drivers/clk/clk_zynq.c > > @@ -434,6 +434,9 @@ static ulong zynq_clk_get_rate(struct clk *clk) > > case lqspi_clk ... pcap_clk: > > case sdio0_clk ... spi1_clk: > > return zynq_clk_get_peripheral_rate(priv, id, 0); > > + case i2c0_aper_clk ... i2c1_aper_clk: > > + return zynq_clk_get_cpu_rate(priv, cpu_1x_clk); > > + > > please remove this empty line. OK. I'll send V2 patch. > > > default: > > return -ENXIO; > > } > > > > I am also curious why you are enabling I2C in SPL. What are you doing > with that? I have to turn on very early some voltage rails on my board, where i have to communicate with i2c to a resetcontroller. > > Thanks, > Michal cheers, Hannes _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
