Am 13.02.2019 um 21:26 schrieb Philipp Tomsich:
On 13.02.2019, at 21:19, Simon Goldschmidt
<simon.k.r.goldschm...@gmail.com
<mailto:simon.k.r.goldschm...@gmail.com>> wrote:
Am 13.02.2019 um 21:13 schrieb Heinrich Schuchardt:
The SPL image for the rk3288 boards has to fit into 32 KiB. This includes
4 KiB for the device tree and up to 2 KiB for the file header.
I'm not related to this board (and don't mean to step against this
patch), but I have similar problems on socfpga (though with 64 KiB,
not 32 KiB) and trying to solve them, so:
How do you know the DTB is 4 KiB maximum? Is there a check for this?
Aside from that, I don't know how it is for rk3288, but socfpga
allocates initial stack, heap and 'gd' into the same RAM, so available
size check should also substract that from my 64 KiB. How is this
handled here?
The RK3288 has ~ 100kB of SRAM, but the BootROM has a size limitation on
loading the SPL stage.
So stack will always be located beyond the end of the SPL.
Aha, so it's not comparable to socfgpa in that respect. Thanks for the info!
Regards,
Simon
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
