Hi all,
I have found something I don't undertand in the codebase, and I hope
someone here can help me out a bit.
I am currently working in a board which uses a MPC8247 processor
(which belongs to the 8272 family) and I was trying to allocate space
from the built-in dual port RAM when I found out the following piece
of code in arch/powerpc/include/asm/cpm_8260.h
79 /* Dual Port RAM addresses. The first 16K is available for almost
80 * any CPM use, so we put the BDs there. The first 128 bytes are
81 * used for SMC1 and SMC2 parameter RAM, so we start allocating
82 * BDs above that. All of this must change when we start
83 * downloading RAM microcode.
84 */
85 #define CPM_DATAONLY_BASE ((uint)128)
86 #define CPM_DP_NOSPACE ((uint)0x7fffffff)
87 #ifndef CONFIG_MPC8272_FAMILY
88 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
89 #define CPM_FCC_SPECIAL_BASE ((uint)0x0000b000)
90 #else /* 8247/48/71/72 */
91 #define CPM_DATAONLY_SIZE ((uint)(4 * 1024) - CPM_DATAONLY_BASE)
92 #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
93 #endif /* !CONFIG_MPC8272_FAMILY */
I needed to allocate exactly 4*1024 bytes but, as it is decribed in
that file, the maximum allowed memory is (4*1024) - 128 for
MPC8272_FAMILY processors
I opened up the specs of the processor and in 13.5 Dual-Port RAM it
reads: "The CPM status RAM (16KByte)... ". And the memory map is (a
dirty plain-text interpretation made by me which I hope can be read) :
0x0000 +----------+ 0x4000 +----------+ 0x8000 +----------+
| | | | | |
| bank #1 | | | | bank #5 |
0x0800 +----------+ | | 0x8800 +----------+
| | | | | |
| bank #2 | | | | bank #6 |
0x1000 +----------+ | | 0x9000 +----------+
| | | | | |
| bank #3 | | | | bank #7 |
0x1800 +----------+ | | 0x9800 +----------+
| | | | | |
| bank #4 | | | | bank #8 |
+----------+ | | +----------+
| | | | | |
| | | | | |
| reserved | | reserved | | reserved |
| | | | | |
It shouldn't be a big deal to change that #define to 1024*8, because
there are at least 4 contiguous banks of 0x800 (2048) bytes of memory
according to the specs. Should that be changed or am I missing
something about that maximum size?
I also had a look at the 2.4 linux kernel sources I am using and in
include/asm-ppc/cpm_8248.h dual port RAM is described as:
/* Dual Port RAM addresses. The first 16K is available for almost
* any CPM use, so we put the BDs there. The first 128 bytes are
* used for SMC1 and SMC2 parameter RAM, so we start allocating
* BDs above that. All of this must change when we start
* downloading RAM microcode.
*/
#define CPM_DATAONLY_BASE ((uint)128)
#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
#define CPM_FCC_SPECIAL_BASE ((uint)0x00008800)
Thanks,
Faustino Frechilla
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