On Mon, 2019-02-11 at 04:32 +0000, Anup Patel wrote: > > -----Original Message----- > > From: Auer, Lukas [mailto:lukas.a...@aisec.fraunhofer.de] > > Sent: Monday, February 11, 2019 12:10 AM > > To: s...@chromium.org; michal.si...@xilinx.com; bmeng...@gmail.com; > > joe.hershber...@ni.com; r...@andestech.com; > > yamada.masah...@socionext.com; mon...@monstr.eu; Anup Patel > > <anup.pa...@wdc.com> > > Cc: paul.walms...@sifive.com; pal...@sifive.com; > > u-boot@lists.denx.de; > > ag...@suse.de; Atish Patra <atish.pa...@wdc.com> > > Subject: Re: [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock > > driver > > > > On Sat, 2019-02-09 at 06:32 +0000, Anup Patel wrote: > > > Add driver code for the SiFive FU540 PRCI IP block. This IP > > > block > > > handles reset and clock control for the SiFive FU540 device and > > > implements SoC-level clock tree controls and dividers. > > > > > > Based on code written by Wesley Terpstra <wes...@sifive.com> > > > found in > > > commit 999529edf517ed75b56659d456d221b2ee56bb60 of: > > > https://github.com/riscv/riscv-linux > > > > > > Boot and PLL rate change were tested on a SiFive HiFive Unleashed > > > board. > > > > > > Signed-off-by: Paul Walmsley <paul.walms...@sifive.com> > > > Signed-off-by: Atish Patra <atish.pa...@wdc.com> > > > Signed-off-by: Anup Patel <anup.pa...@wdc.com> > > > Reviewed-by: Alexander Graf <ag...@suse.de> > > > --- > > > drivers/clk/Kconfig | 1 + > > > drivers/clk/Makefile | 1 + > > > drivers/clk/sifive/Kconfig | 19 + > > > drivers/clk/sifive/Makefile | 5 + > > > .../clk/sifive/analogbits-wrpll-cln28hpc.h | 101 +++ > > > drivers/clk/sifive/fu540-prci.c | 604 > > > ++++++++++++++++++ > > > drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++++++++++ > > > include/dt-bindings/clk/sifive-fu540-prci.h | 29 + > > > 8 files changed, 1150 insertions(+) > > > create mode 100644 drivers/clk/sifive/Kconfig create mode > > > 100644 > > > drivers/clk/sifive/Makefile create mode 100644 > > > drivers/clk/sifive/analogbits-wrpll-cln28hpc.h > > > create mode 100644 drivers/clk/sifive/fu540-prci.c create mode > > > 100644 drivers/clk/sifive/wrpll-cln28hpc.c > > > create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h > > > > > > > This patch currently does not apply cleanly on U-Boot master. > > The patches are based upon latest RISC-V U-Boot tree > (git://git.denx.de/u-boot-riscv.git) at commit id > 91882c472d8c0aef4db699d3f2de55bf43d4ae4b > > Do you want me to base this upon U-Boot master ?? > > Regards, > Anup
Yes, that's what I meant. The series applies cleanly now, thanks! Lukas _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
