On Sat, 2019-02-09 at 06:32 +0000, Anup Patel wrote: > Add driver code for the SiFive FU540 PRCI IP block. This IP block > handles reset and clock control for the SiFive FU540 device and > implements SoC-level clock tree controls and dividers. > > Based on code written by Wesley Terpstra <wes...@sifive.com> > found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: > https://github.com/riscv/riscv-linux > > Boot and PLL rate change were tested on a SiFive HiFive Unleashed > board. > > Signed-off-by: Paul Walmsley <paul.walms...@sifive.com> > Signed-off-by: Atish Patra <atish.pa...@wdc.com> > Signed-off-by: Anup Patel <anup.pa...@wdc.com> > Reviewed-by: Alexander Graf <ag...@suse.de> > --- > drivers/clk/Kconfig | 1 + > drivers/clk/Makefile | 1 + > drivers/clk/sifive/Kconfig | 19 + > drivers/clk/sifive/Makefile | 5 + > .../clk/sifive/analogbits-wrpll-cln28hpc.h | 101 +++ > drivers/clk/sifive/fu540-prci.c | 604 > ++++++++++++++++++ > drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++++++++++ > include/dt-bindings/clk/sifive-fu540-prci.h | 29 + > 8 files changed, 1150 insertions(+) > create mode 100644 drivers/clk/sifive/Kconfig > create mode 100644 drivers/clk/sifive/Makefile > create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h > create mode 100644 drivers/clk/sifive/fu540-prci.c > create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c > create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h >
This patch currently does not apply cleanly on U-Boot master. Thanks, Lukas _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
