On 31/01/19 6:48 PM, Jagan Teki wrote: > On Tue, Jan 29, 2019 at 11:28 AM Vignesh R <vigne...@ti.com> wrote: >> >> Now that new SPI NOR layer uses stateless 4 byte opcodes by default, >> don't enable SPI_FLASH_BAR. For SPI controllers that cannot support >> 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, >> renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to >> not break functionality. >> >> Signed-off-by: Vignesh R <vigne...@ti.com> >> Tested-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com> >> Tested-by: Stefan Roese <s...@denx.de> >> Tested-by: Horatiu Vultur <horatiu.vul...@microchip.com> >> --- >> arch/arm/mach-omap2/am33xx/Kconfig | 1 - >> configs/alt_defconfig | 1 - >> configs/am57xx_evm_defconfig | 1 - >> configs/am57xx_hs_evm_defconfig | 1 - >> configs/ap121_defconfig | 1 - >> configs/ap143_defconfig | 1 - >> configs/avnet_ultra96_rev1_defconfig | 1 - >> configs/axs101_defconfig | 1 - >> configs/axs103_defconfig | 1 - >> configs/bg0900_defconfig | 1 - >> configs/blanche_defconfig | 1 - >> configs/cl-som-am57x_defconfig | 1 - >> configs/clearfog_defconfig | 1 - >> configs/cm_t43_defconfig | 1 - >> configs/db-88f6820-amc_defconfig | 1 - >> configs/display5_defconfig | 1 - >> configs/display5_factory_defconfig | 1 - >> configs/dra7xx_evm_defconfig | 1 - >> configs/dra7xx_hs_evm_defconfig | 1 - >> configs/ds109_defconfig | 1 - >> configs/ds414_defconfig | 1 - >> configs/evb-rv1108_defconfig | 1 - >> configs/gose_defconfig | 1 - >> configs/helios4_defconfig | 1 - >> configs/k2g_evm_defconfig | 1 - >> configs/k2g_hs_evm_defconfig | 1 - >> configs/koelsch_defconfig | 1 - >> configs/lager_defconfig | 1 - >> configs/maxbcm_defconfig | 1 - >> configs/mt7629_rfb_defconfig | 1 - >> configs/mx6sxsabreauto_defconfig | 1 - >> configs/mx6sxsabresd_defconfig | 1 - >> configs/mx6ul_14x14_evk_defconfig | 1 - >> configs/mx6ul_9x9_evk_defconfig | 1 - >> configs/mx6ull_14x14_evk_defconfig | 1 - >> configs/mx6ull_14x14_evk_plugin_defconfig | 1 - >> configs/mx7dsabresd_qspi_defconfig | 1 - >> configs/porter_defconfig | 1 - >> configs/r8a77970_eagle_defconfig | 1 - >> configs/silk_defconfig | 1 - >> configs/socfpga_arria5_defconfig | 1 - >> configs/socfpga_cyclone5_defconfig | 1 - >> configs/socfpga_is1_defconfig | 1 - >> configs/socfpga_sockit_defconfig | 1 - >> configs/socfpga_socrates_defconfig | 1 - >> configs/socfpga_sr1500_defconfig | 1 - >> configs/socfpga_stratix10_defconfig | 1 - >> configs/stout_defconfig | 1 - >> configs/topic_miami_defconfig | 1 - >> configs/topic_miamilite_defconfig | 1 - >> configs/topic_miamiplus_defconfig | 1 - >> configs/xilinx_versal_virt_defconfig | 1 - >> configs/xilinx_zynqmp_mini_qspi_defconfig | 1 - >> configs/xilinx_zynqmp_zc1232_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zc1254_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zc1275_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zc1275_revB_defconfig | 1 - >> configs/xilinx_zynqmp_zc1751_xm015_dc1_defconfig | 1 - >> configs/xilinx_zynqmp_zc1751_xm016_dc2_defconfig | 1 - >> configs/xilinx_zynqmp_zc1751_xm018_dc4_defconfig | 1 - >> configs/xilinx_zynqmp_zcu100_revC_defconfig | 1 - >> configs/xilinx_zynqmp_zcu102_rev1_0_defconfig | 1 - >> configs/xilinx_zynqmp_zcu102_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zcu102_revB_defconfig | 1 - >> configs/xilinx_zynqmp_zcu104_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zcu104_revC_defconfig | 1 - >> configs/xilinx_zynqmp_zcu106_revA_defconfig | 1 - >> configs/xilinx_zynqmp_zcu111_revA_defconfig | 1 - >> configs/zynq_cc108_defconfig | 1 - >> configs/zynq_cse_qspi_defconfig | 1 - >> configs/zynq_dlc20_rev1_0_defconfig | 1 - >> configs/zynq_microzed_defconfig | 1 - >> configs/zynq_minized_defconfig | 1 - >> configs/zynq_z_turn_defconfig | 1 - >> configs/zynq_zc702_defconfig | 1 - >> configs/zynq_zc706_defconfig | 1 - >> configs/zynq_zc770_xm010_defconfig | 1 - >> configs/zynq_zc770_xm013_defconfig | 1 - >> configs/zynq_zed_defconfig | 1 - >> configs/zynq_zybo_defconfig | 1 - >> configs/zynq_zybo_z7_defconfig | 1 - > > zynq targets do need BAR, same has commented in previous mails.
Hmmm, Is this a limitation of SPI controller on the SoC or flash on the board? AFAICS, zynq_spi.c, zynq_qspi.c zynq_spi.c zynqmp_gqspi.c are all FIFO based SPI controllers and ideally should not care about address length. Could you please explain why BAR is a requirement on these platforms? Were you able to test this series on any of those platforms? Regards Vignesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
