On Fri, 2019-01-18 at 11:18 +0000, Anup Patel wrote:
> The QEMU CPU support under arch/riscv is pretty much generic
> and works fine for SiFive Unleashed as well. In fact, there
> will be quite a few RISC-V SOCs for which QEMU CPU support
> will work fine.
>
> This patch renames cpu/qemu to cpu/generic to indicate the
> above fact. If there are SOC specific errata workarounds
> required in cpu/generic then those can be done at runtime
> in cpu/generic based on CPU vendor specific DT compatible
> string.
>
> Signed-off-by: Anup Patel <anup.pa...@wdc.com>
> Reviewed-by: Alexander Graf <ag...@suse.de>
> ---
> arch/riscv/Kconfig | 2 +-
> arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +-
> arch/riscv/cpu/{qemu => generic}/Makefile | 0
> arch/riscv/cpu/{qemu => generic}/cpu.c | 0
> arch/riscv/cpu/{qemu => generic}/dram.c | 0
> board/emulation/qemu-riscv/Kconfig | 4 ++--
> 6 files changed, 4 insertions(+), 4 deletions(-)
> rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
> rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
> rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
> rename arch/riscv/cpu/{qemu => generic}/dram.c (100%)
>
Reviewed-by: Lukas Auer <lukas.a...@aisec.fraunhofer.de>
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