>
> Michael Zaidman <michael.zaid...@gmail.com> wrote on 2010/04/16 18:44:12:
> >
> > On Fri, Apr 16, 2010 at 1:25 AM, Kim Phillips
> > <kim.phill...@freescale.com> wrote:
> > > On Thu, 8 Apr 2010 10:37:08 +0200
> > > Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote:
> > >
> > >> Kim Phillips <kim.phill...@freescale.com> wrote on 2010-04-08 10:27:03:
>
> > Although this is good for most of the cases it does not fit in the
> > algorithm implemented in the post_ecc_test. The first stw in
> > ppcDWstore will generate ecc error (due to read-modify-write) so ecc
> > capture data registers will capture only first word as it was written
> > with flipped injected error bit or without depending on its position
> > in the data_error_inject_hi or data_error_inject_lo injection mask
> > registers. The second ecc capture data word will hold the data that
> > was in the memory right before the ppcDWstore call. Thus, the test
> > validation while working for stfd will fail for stw x 2. So, the
> > algorithm need to be reworked...
> >
> > I also agree with Joakim regarding the routine call overhead and
> > replacing it by inline macro. Please review this code.
> >
> > From 5a64a5c4f480dcea89bc8f13f8464b96b888b73c Mon Sep 17 00:00:00 2001
> > From: Michael Zaidman <michael.zaid...@gmail.com>
> > Date: Fri, 16 Apr 2010 18:50:43 +0300
> > Subject: [U-Boot][PATCH] asm-ppc/io.h - added 64bits I/O accessors for
> > ppc32.
> >
> > Suggested-by: Joakim Tjernlund <joakim.tjernl...@transmode.se>
> > Signed-off-by: Michael Zaidman <michael.zaid...@gmail.com>
> > ---
> > include/asm-ppc/io.h | 49
> > +++++++++++++++++++++++++++++++++++++++++++++++++
> > 1 files changed, 49 insertions(+), 0 deletions(-)
> >
> > diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
> > index 4ddad26..0d5e125 100644
> > --- a/include/asm-ppc/io.h
> > +++ b/include/asm-ppc/io.h
> > @@ -231,6 +231,31 @@ extern inline unsigned in_be32(const volatile
> > unsigned __iomem *addr)
> > return ret;
> > }
> >
> > +/* 64 bits I/O read accessor for ppc32 */
> > +extern inline void in_be64(volatile unsigned __iomem *addr, volatile
> > unsigned __iomem *ret)
> > +{
> > +/* FIXME: Add other CPUs without FPU here... */
> > +#if defined(CONFIG_MPC832x)
> > + __asm__ __volatile__(
> > + "sync\n"
> > + "lwz%U0%X0 0,%0\n"
> > + "stw%U1%X1 0,%1\n"
> > + "lwz%U0%X0 0,4+%0\n"
> > + "stw%U1%X1 0,4+%1\n"
> > + "isync"
> > + :"=m" (*ret)
> > + :"m" (*addr), "r" (addr), "r" (ret));
>
> To emulate FP better you should do 2 loads first and then 2 stores.
> It is also faster.
Forgot, you can add the MPC8xx CPU's too. These are also without FPU.
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