On Fri, Apr 16, 2010 at 1:25 AM, Kim Phillips
<kim.phill...@freescale.com> wrote:
> On Thu, 8 Apr 2010 10:37:08 +0200
> Joakim Tjernlund <joakim.tjernl...@transmode.se> wrote:
>
>> Kim Phillips <kim.phill...@freescale.com> wrote on 2010-04-08 10:27:03:
>> >
>> > The documentation is confusing: the e300c2 has its FPU chopped off -
>> > the FP registers are simply not there.
>> >
>> > this is a good catch by Jocke - it would be best if generic 83xx code
>> > didn't depend on the ppcDW* accessors.
>>
>> That or one could impl. ppcDW* using normal load/store insns for 832x.
>> Either way the ppcDW* should be inlined as the overhead for doing
>> function calls isn't something you want when looking for speed.
>
> another good point, but it seems they were added primarily for code
> density benefits. I think we can do something like this in the
> meantime:
>
> From 686d3bb7a732ec36beec169c4eaf4882382d3aa2 Mon Sep 17 00:00:00 2001
> From: Kim Phillips <kim.phill...@freescale.com>
> Date: Thu, 8 Apr 2010 18:22:13 -0500
> Subject: [PATCH] mpc83xx: implement ppcDW{load,store} accessors for e300c2
>
> e300c2 core based processors (MPC832x) don't have an FPU: provide
> alternative, gpr based accessor functions for code compatibility.
>
> Suggested-by: Joakim Tjernlund <joakim.tjernl...@transmode.se>
> Signed-off-by: Kim Phillips <kim.phill...@freescale.com>
> ---
> arch/ppc/cpu/mpc83xx/start.S | 14 ++++++++++++++
> 1 files changed, 14 insertions(+), 0 deletions(-)
>
> diff --git a/arch/ppc/cpu/mpc83xx/start.S b/arch/ppc/cpu/mpc83xx/start.S
> index 68bb620..6bfce57 100644
> --- a/arch/ppc/cpu/mpc83xx/start.S
> +++ b/arch/ppc/cpu/mpc83xx/start.S
> @@ -139,14 +139,28 @@ get_pvr:
>
> .globl ppcDWstore
> ppcDWstore:
> +#if !defined(CONFIG_MPC832x)
> lfd 1, 0(r4)
> stfd 1, 0(r3)
> +#else
> + lwz r5, 0(r4)
> + stw r5, 0(r3)
> + lwz r5, 4(r4)
> + stw r5, 4(r3)
> +#endif
> blr
>
> .globl ppcDWload
> ppcDWload:
> +#if !defined(CONFIG_MPC832x)
> lfd 1, 0(r3)
> stfd 1, 0(r4)
> +#else
> + lwz r5, 0(r3)
> + stw r5, 0(r4)
> + lwz r5, 4(r3)
> + stw r5, 4(r4)
> +#endif
> blr
>
> #ifndef CONFIG_DEFAULT_IMMR
> --
> 1.7.0.5
>
Although this is good for most of the cases it does not fit in the
algorithm implemented in the post_ecc_test. The first stw in
ppcDWstore will generate ecc error (due to read-modify-write) so ecc
capture data registers will capture only first word as it was written
with flipped injected error bit or without depending on its position
in the data_error_inject_hi or data_error_inject_lo injection mask
registers. The second ecc capture data word will hold the data that
was in the memory right before the ppcDWstore call. Thus, the test
validation while working for stfd will fail for stw x 2. So, the
algorithm need to be reworked...
I also agree with Joakim regarding the routine call overhead and
replacing it by inline macro. Please review this code.
>From 5a64a5c4f480dcea89bc8f13f8464b96b888b73c Mon Sep 17 00:00:00 2001
From: Michael Zaidman <michael.zaid...@gmail.com>
Date: Fri, 16 Apr 2010 18:50:43 +0300
Subject: [U-Boot][PATCH] asm-ppc/io.h - added 64bits I/O accessors for ppc32.
Suggested-by: Joakim Tjernlund <joakim.tjernl...@transmode.se>
Signed-off-by: Michael Zaidman <michael.zaid...@gmail.com>
---
include/asm-ppc/io.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 49 insertions(+), 0 deletions(-)
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 4ddad26..0d5e125 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -231,6 +231,31 @@ extern inline unsigned in_be32(const volatile
unsigned __iomem *addr)
return ret;
}
+/* 64 bits I/O read accessor for ppc32 */
+extern inline void in_be64(volatile unsigned __iomem *addr, volatile
unsigned __iomem *ret)
+{
+/* FIXME: Add other CPUs without FPU here... */
+#if defined(CONFIG_MPC832x)
+ __asm__ __volatile__(
+ "sync\n"
+ "lwz%U0%X0 0,%0\n"
+ "stw%U1%X1 0,%1\n"
+ "lwz%U0%X0 0,4+%0\n"
+ "stw%U1%X1 0,4+%1\n"
+ "isync"
+ :"=m" (*ret)
+ :"m" (*addr), "r" (addr), "r" (ret));
+#else
+ __asm__ __volatile__(
+ "sync\n"
+ "lfd%U0%X0 1,%0\n"
+ "stfd%U1%X1 1,%1\n"
+ "isync"
+ :"=m" (*ret)
+ :"m" (*addr), "r" (addr), "r" (ret));
+#endif
+}
+
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
@@ -242,6 +267,30 @@ extern inline void out_be32(volatile unsigned
__iomem *addr, int val)
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r"
(val));
}
+/* 64 bits I/O write accessor for ppc32 */
+extern inline void out_be64(volatile unsigned __iomem *addr, volatile
unsigned __iomem *val)
+{
+/* FIXME: Add other CPUs without FPU here... */
+#if defined(CONFIG_MPC832x)
+ __asm__ __volatile__(
+ "sync\n"
+ "lwz%U0%X0 0,%0\n"
+ "stw%U1%X1 0,%1\n"
+ "lwz%U0%X0 0,4+%0\n"
+ "stw%U1%X1 0,4+%1\n"
+ "isync"
+ :"=m" (*addr)
+ :"m" (*val), "r" (addr), "r" (val));
+#else
+ __asm__ __volatile__(
+ "sync\n"
+ "lfd%U1%X1 1,%1\n"
+ "stfd%U0%X0 1,%0"
+ :"=m" (*addr)
+ :"m" (*val), "r" (addr), "r" (val));
+#endif
+}
+
/* Clear and set bits in one shot. These macros can be used to clear and
* set multiple bits in a register using a single call. These macros can
* also be used to set a multiple-bit bit pattern using a mask, by
--
1.6.3.3
>
> but 83xx is still missing (at least) the post_word_{load,store} functions:
[snip]
> Michael, can you resubmit something more comprehensive, something that
> builds for 83xx with CONFIG_POST turned on?
>
Sure.
-michael
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