This patch extends the vf610 DDR memory controller code to support SW
leveling.
Signed-off-by: Lukasz Majewski <lu...@denx.de>
Reviewed-by: Stefan Agner <stefan.ag...@toradex.com>
---
Changes in v2:
- Remove not needed #ifdef
arch/arm/mach-imx/ddrmc-vf610.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index ea6a49e0fa..2f59ec907f 100644
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -10,6 +10,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-vf610.h>
#include <asm/arch/ddrmc-vf610.h>
+#include "ddrmc-vf610-calibration.h"
void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
{
@@ -233,4 +234,8 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const
*timings,
while (!(readl(&ddrmr->cr[80]) & 0x100))
udelay(10);
+
+#ifdef CONFIG_DDRMC_VF610_CALIBRATION
+ ddrmc_calibration(ddrmr);
+#endif
}
--
2.11.0
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