On 11/01/2018 12:39 PM, Masahiro Yamada wrote: > On Thu, Nov 1, 2018 at 2:22 AM Marek Vasut <marek.va...@gmail.com> wrote: >> >> The TMIO core has a quirk where divider == 1 must not be set in DDR modes. >> Handle this by setting divider to 2, as suggested in the documentation. >> >> Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com> >> Cc: Masahiro Yamada <yamada.masah...@socionext.com> >> --- >> drivers/mmc/tmio-common.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/drivers/mmc/tmio-common.c b/drivers/mmc/tmio-common.c >> index 9eb2984ed3..072171d4b3 100644 >> --- a/drivers/mmc/tmio-common.c >> +++ b/drivers/mmc/tmio-common.c >> @@ -565,6 +565,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv >> *priv, >> >> divisor = DIV_ROUND_UP(mclk, mmc->clock); >> >> + /* Do not set divider to 0xff in DDR mode */ >> + if (mmc->ddr_mode && (divisor == 1)) >> + divisor = 2; >> + > > With this patch applied, my board would not boot any more. > > Please stop adding Renesas-specific quirks to tmio-common. > > By moving tmio_sd_set_clk_rate to a platform hook, > you can do anything you want to do in renesas-sdhi.c
Are you sure this is renesas-specific ? My understanding is this is common to SDHI. I am happy to pull this whole thing into renesas specific part of the driver, but then you won't get all the clock fixes and there'll be duplication of code. -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
