Add R5 specific dts for am654-evm.
Reviewed-by: Tom Rini <tr...@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Signed-off-by: Andreas Dannenberg <dannenb...@ti.com>
Signed-off-by: Keerthy <j-keer...@ti.com>
---
arch/arm/dts/Makefile | 2 +-
.../dts/k3-am654-base-board-ddr4-1333MHz.dtsi | 195 ++++++++++++++
arch/arm/dts/k3-am654-ddr.dtsi | 241 ++++++++++++++++++
arch/arm/dts/k3-am654-r5-base-board.dts | 139 ++++++++++
4 files changed, 576 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi
create mode 100644 arch/arm/dts/k3-am654-ddr.dtsi
create mode 100644 arch/arm/dts/k3-am654-r5-base-board.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0de6234eec..821a3d79ea 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -554,7 +554,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
stm32mp157c-ed1.dtb \
stm32mp157c-ev1.dtb
-dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
+dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi
b/arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi
new file mode 100644
index 0000000000..c07e6519e5
--- /dev/null
+++ b/arch/arm/dts/k3-am654-base-board-ddr4-1333MHz.dtsi
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#define DDRCTL_DFIMISC 0x00000000
+#define DDRCTL_DFITMG0 0x04878206
+#define DDRCTL_DFITMG1 0x00060606
+#define DDRCTL_DFITMG2 0x00000504
+#define DDRCTL_INIT0 0x400100A3
+#define DDRCTL_INIT1 0x00420000
+#define DDRCTL_INIT2 0x00000000
+#define DDRCTL_INIT3 0x00100501
+#define DDRCTL_INIT4 0x00000020
+#define DDRCTL_INIT5 0x00100000
+#define DDRCTL_INIT6 0x00000480
+#define DDRCTL_INIT7 0x00000097
+#define DDRCTL_MSTR 0x41040010
+#define DDRCTL_ODTCFG 0x06000608
+#define DDRCTL_ODTMAP 0x00000001
+#define DDRCTL_RANKCTL 0x00000000
+#define DDRCTL_RFSHCTL0 0x00210070
+#define DDRCTL_RFSHCTL3 0x00000000
+#define DDRCTL_RFSHTMG 0x00510075
+#define DDRCTL_STAT 0x00000000
+#define DDRCTL_SWCTL 0x00000000
+#define DDRCTL_SWSTAT 0x00000000
+#define DDRCTL_ZQCTL0 0x21000040
+#define DDRCTL_ZQCTL1 0x00027bc8
+#define DDRCTL_CRCPARCTL0 0x1A000000
+#define DDRCTL_CRCPARCTL1 0x0048051E
+#define DDRCTL_ECCCFG0 0x00000000
+#define DDRCTL_ADDRMAP0 0x001F1F1F
+#define DDRCTL_ADDRMAP1 0x003f0808
+#define DDRCTL_ADDRMAP2 0x00000000
+#define DDRCTL_ADDRMAP3 0x00000000
+#define DDRCTL_ADDRMAP4 0x00001f1f
+#define DDRCTL_ADDRMAP5 0x08080808
+#define DDRCTL_ADDRMAP6 0x08080808
+#define DDRCTL_ADDRMAP7 0x00000f0f
+#define DDRCTL_ADDRMAP8 0x00000a0a
+#define DDRCTL_ADDRMAP9 0x0000000
+#define DDRCTL_ADDRMAP10 0x0000000
+#define DDRCTL_ADDRMAP11 0x001f1f00
+#define DDRCTL_DQMAP0 0x00000000
+#define DDRCTL_DQMAP1 0x00000000
+#define DDRCTL_DQMAP4 0x00000000
+#define DDRCTL_DQMAP5 0x00000000
+#define DDRCTL_PWRCTL 0x00000000
+#define DDRCTL_DRAMTMG0 0x0b0a160b
+#define DDRCTL_DRAMTMG1 0x00020310
+#define DDRCTL_DRAMTMG2 0x0506040a
+#define DDRCTL_DRAMTMG3 0x0000400C
+#define DDRCTL_DRAMTMG4 0x05020205
+#define DDRCTL_DRAMTMG5 0x04040302
+#define DDRCTL_DRAMTMG6 0x0000000
+#define DDRCTL_DRAMTMG7 0x00000000
+#define DDRCTL_DRAMTMG8 0x02020C04
+#define DDRCTL_DRAMTMG9 0x00020208
+#define DDRCTL_DRAMTMG11 0x1005010E
+#define DDRCTL_DRAMTMG12 0x00000008
+#define DDRCTL_DRAMTMG13 0x00000000
+#define DDRCTL_DRAMTMG14 0x00000000
+#define DDRCTL_DRAMTMG15 0x00000035
+#define DDRCTL_DRAMTMG17 0x00000000
+#define DDRPHY_DCR 0x0000040C
+#define DDRPHY_DSGCR 0x02A0C129
+#define DDRPHY_DX0GCR0 0x00000000
+#define DDRPHY_DX0GCR1 0x00000000
+#define DDRPHY_DX0GCR2 0x00000000
+#define DDRPHY_DX0GCR3 0x00000000
+#define DDRPHY_DX0GCR4 0x0E00c93C
+#define DDRPHY_DX0GCR5 0x00000049
+#define DDRPHY_DX0GSR0 0x00000000
+#define DDRPHY_DX0GSR1 0x00000000
+#define DDRPHY_DX0GSR2 0x00000000
+#define DDRPHY_DX0GSR3 0x00000000
+#define DDRPHY_DX0GSR4 0x00000000
+#define DDRPHY_DX0GSR5 0x00000000
+#define DDRPHY_DX0GSR6 0x00000000
+#define DDRPHY_DX0GTR0 0x00020002
+#define DDRPHY_DX1GCR0 0x00000000
+#define DDRPHY_DX1GCR1 0x00000000
+#define DDRPHY_DX1GCR2 0x00000000
+#define DDRPHY_DX1GCR3 0x00000000
+#define DDRPHY_DX1GCR4 0x0E00c93C
+#define DDRPHY_DX1GCR5 0x00000049
+#define DDRPHY_DX1GSR0 0x00000000
+#define DDRPHY_DX1GSR1 0x00000000
+#define DDRPHY_DX1GSR2 0x00000000
+#define DDRPHY_DX1GSR3 0x00000000
+#define DDRPHY_DX1GSR4 0x00000000
+#define DDRPHY_DX1GSR5 0x00000000
+#define DDRPHY_DX1GSR6 0x00000000
+#define DDRPHY_DX1GTR0 0x00020002
+#define DDRPHY_DX2GCR0 0x00000000
+#define DDRPHY_DX2GCR1 0x00000000
+#define DDRPHY_DX2GCR2 0x00000000
+#define DDRPHY_DX2GCR3 0x00000000
+#define DDRPHY_DX2GCR4 0x0E00c93C
+#define DDRPHY_DX2GCR5 0x00000049
+#define DDRPHY_DX2GSR0 0x00000000
+#define DDRPHY_DX2GSR1 0x00000000
+#define DDRPHY_DX2GSR2 0x00000000
+#define DDRPHY_DX2GSR3 0x00000000
+#define DDRPHY_DX2GSR4 0x00000000
+#define DDRPHY_DX2GSR5 0x00000000
+#define DDRPHY_DX2GSR6 0x00000000
+#define DDRPHY_DX2GTR0 0x00020002
+#define DDRPHY_DX3GCR0 0x00000000
+#define DDRPHY_DX3GCR1 0x00000000
+#define DDRPHY_DX3GCR2 0x00000000
+#define DDRPHY_DX3GCR3 0x00000000
+#define DDRPHY_DX3GCR4 0x0E00c93C
+#define DDRPHY_DX3GCR5 0x00000049
+#define DDRPHY_DX3GSR0 0x00000000
+#define DDRPHY_DX3GSR1 0x00000000
+#define DDRPHY_DX3GSR2 0x00000000
+#define DDRPHY_DX3GSR3 0x00000000
+#define DDRPHY_DX3GSR4 0x00000000
+#define DDRPHY_DX3GSR5 0x00000000
+#define DDRPHY_DX3GSR6 0x00000000
+#define DDRPHY_DX3GTR0 0x00020002
+#define DDRPHY_DX4GCR0 0x40703260
+#define DDRPHY_DX4GCR1 0x55556000
+#define DDRPHY_DX4GCR2 0xaaaa0000
+#define DDRPHY_DX4GCR3 0xffe18587
+#define DDRPHY_DX4GCR4 0x00000000
+#define DDRPHY_DX4GCR5 0x00000000
+#define DDRPHY_DX4GSR0 0x00000000
+#define DDRPHY_DX4GSR1 0x00000000
+#define DDRPHY_DX4GSR2 0x00000000
+#define DDRPHY_DX4GSR3 0x00000000
+#define DDRPHY_DX4GSR4 0x00000000
+#define DDRPHY_DX4GSR5 0x00000000
+#define DDRPHY_DX4GSR6 0x00000000
+#define DDRPHY_DX4GTR0 0x00000000
+#define DDRPHY_DX8SL0DQSCTL 0x00000000
+#define DDRPHY_DX8SL0DXCTL2 0x00141830
+#define DDRPHY_DX8SL0IOCR 0x04800000
+#define DDRPHY_DX8SL0PLLCR0 0x021c4000
+#define DDRPHY_DX8SL1DQSCTL 0x00000000
+#define DDRPHY_DX8SL1DXCTL2 0x00141830
+#define DDRPHY_DX8SL1IOCR 0x04800000
+#define DDRPHY_DX8SL1PLLCR0 0x021c4000
+#define DDRPHY_DX8SL2DQSCTL 0x00000000
+#define DDRPHY_DX8SL2DXCTL2 0x00141830
+#define DDRPHY_DX8SL2IOCR 0x04800000
+#define DDRPHY_DX8SL2PLLCR0 0x021c4000
+#define DDRPHY_DXCCR 0x00000038
+#define DDRPHY_ODTCR 0x00010000
+#define DDRPHY_PGCR0 0x00000000
+#define DDRPHY_PGCR1 0x020046C0
+#define DDRPHY_PGCR2 0x00F09f60
+#define DDRPHY_PGCR3 0x55AA0080
+#define DDRPHY_PGCR5 0x01010004
+#define DDRPHY_PGCR6 0x00013001
+#define DDRPHY_PGSR0 0x00000000
+#define DDRPHY_DTCR0 0x8000B1c7
+#define DDRPHY_DTCR1 0x00010236
+#define DDRPHY_MR0 0x00000010
+#define DDRPHY_MR1 0x00000501
+#define DDRPHY_MR2 0x00000000
+#define DDRPHY_MR3 0x00000020
+#define DDRPHY_MR4 0x00000000
+#define DDRPHY_MR5 0x00000480
+#define DDRPHY_MR6 0x00000097
+#define DDRPHY_MR11 0x00000000
+#define DDRPHY_MR12 0x00000000
+#define DDRPHY_MR13 0x00000000
+#define DDRPHY_MR14 0x00000000
+#define DDRPHY_MR22 0x00000000
+#define DDRPHY_PIR 0x00000000
+#define DDRPHY_PLLCR0 0x021c4000
+#define DDRPHY_RANKIDR 0x0000000
+#define DDRPHY_VTCR0 0xF3C32017
+#define DDRPHY_ACIOCR5 0x04800000
+#define DDRPHY_IOVCR0 0x0F0C0C0C
+#define DDRPHY_DTPR0 0x04160905
+#define DDRPHY_DTPR1 0x28140000
+#define DDRPHY_DTPR2 0x00040300
+#define DDRPHY_DTPR3 0x02800000
+#define DDRPHY_DTPR4 0x00ea0704
+#define DDRPHY_DTPR5 0x001f0905
+#define DDRPHY_DTPR6 0x00000505
+#define DDRPHY_PTR2 0x00000000
+#define DDRPHY_PTR3 0x00061A80
+#define DDRPHY_PTR4 0x000000E0
+#define DDRPHY_PTR5 0x00027100
+#define DDRPHY_PTR6 0x04000320
+#define DDRPHY_ZQCR 0x008A2A58
+#define DDRPHY_ZQ0PR0 0x000077DD
+#define DDRPHY_ZQ1PR0 0x000077DD
+#define DDRPHY_ZQ2PR0 0x000077DD
+#define DDRPHY_ZQ3PR0 0x000077DD
diff --git a/arch/arm/dts/k3-am654-ddr.dtsi b/arch/arm/dts/k3-am654-ddr.dtsi
new file mode 100644
index 0000000000..47272df91e
--- /dev/null
+++ b/arch/arm/dts/k3-am654-ddr.dtsi
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/ {
+ memorycontroller: memorycontroller@0298e000 {
+ compatible = "ti,am654-ddrss";
+ reg = <0x0 0x0298e000 0x0 0x200>,
+ <0x0 0x02980000 0x0 0x4000>,
+ <0x0 0x02988000 0x0 0x2000>;
+ reg-names = "ss", "ctl", "phy";
+ clocks = <&k3_clks 20 0>;
+ power-domains = <&k3_pds 20>,
+ <&k3_pds 244>;
+ u-boot,dm-spl;
+
+ ti,ctl-reg = <
+ DDRCTL_DFIMISC
+ DDRCTL_DFITMG0
+ DDRCTL_DFITMG1
+ DDRCTL_DFITMG2
+ DDRCTL_INIT0
+ DDRCTL_INIT1
+ DDRCTL_INIT2
+ DDRCTL_INIT3
+ DDRCTL_INIT4
+ DDRCTL_INIT5
+ DDRCTL_INIT6
+ DDRCTL_INIT7
+ DDRCTL_MSTR
+ DDRCTL_ODTCFG
+ DDRCTL_ODTMAP
+ DDRCTL_RANKCTL
+ DDRCTL_RFSHCTL0
+ DDRCTL_RFSHCTL3
+ DDRCTL_RFSHTMG
+ DDRCTL_STAT
+ DDRCTL_SWCTL
+ DDRCTL_SWSTAT
+ DDRCTL_ZQCTL0
+ DDRCTL_ZQCTL1
+ >;
+
+ ti,ctl-crc = <
+ DDRCTL_CRCPARCTL0
+ DDRCTL_CRCPARCTL1
+ >;
+
+ ti,ctl-ecc = <
+ DDRCTL_ECCCFG0
+ >;
+
+ ti,ctl-map = <
+ DDRCTL_ADDRMAP0
+ DDRCTL_ADDRMAP1
+ DDRCTL_ADDRMAP2
+ DDRCTL_ADDRMAP3
+ DDRCTL_ADDRMAP4
+ DDRCTL_ADDRMAP5
+ DDRCTL_ADDRMAP6
+ DDRCTL_ADDRMAP7
+ DDRCTL_ADDRMAP8
+ DDRCTL_ADDRMAP9
+ DDRCTL_ADDRMAP10
+ DDRCTL_ADDRMAP11
+ DDRCTL_DQMAP0
+ DDRCTL_DQMAP1
+ DDRCTL_DQMAP4
+ DDRCTL_DQMAP5
+ >;
+
+ ti,ctl-pwr = <
+ DDRCTL_PWRCTL
+ >;
+
+ ti,ctl-timing = <
+ DDRCTL_DRAMTMG0
+ DDRCTL_DRAMTMG1
+ DDRCTL_DRAMTMG2
+ DDRCTL_DRAMTMG3
+ DDRCTL_DRAMTMG4
+ DDRCTL_DRAMTMG5
+ DDRCTL_DRAMTMG6
+ DDRCTL_DRAMTMG7
+ DDRCTL_DRAMTMG8
+ DDRCTL_DRAMTMG9
+ DDRCTL_DRAMTMG11
+ DDRCTL_DRAMTMG12
+ DDRCTL_DRAMTMG13
+ DDRCTL_DRAMTMG14
+ DDRCTL_DRAMTMG15
+ DDRCTL_DRAMTMG17
+ >;
+
+ ti,phy-cfg = <
+ DDRPHY_DCR
+ DDRPHY_DSGCR
+ DDRPHY_DX0GCR0
+ DDRPHY_DX0GCR1
+ DDRPHY_DX0GCR2
+ DDRPHY_DX0GCR3
+ DDRPHY_DX0GCR4
+ DDRPHY_DX0GCR5
+ DDRPHY_DX0GSR0
+ DDRPHY_DX0GSR1
+ DDRPHY_DX0GSR2
+ DDRPHY_DX0GSR3
+ DDRPHY_DX0GSR4
+ DDRPHY_DX0GSR5
+ DDRPHY_DX0GSR6
+ DDRPHY_DX0GTR0
+ DDRPHY_DX1GCR0
+ DDRPHY_DX1GCR1
+ DDRPHY_DX1GCR2
+ DDRPHY_DX1GCR3
+ DDRPHY_DX1GCR4
+ DDRPHY_DX1GCR5
+ DDRPHY_DX1GSR0
+ DDRPHY_DX1GSR1
+ DDRPHY_DX1GSR2
+ DDRPHY_DX1GSR3
+ DDRPHY_DX1GSR4
+ DDRPHY_DX1GSR5
+ DDRPHY_DX1GSR6
+ DDRPHY_DX1GTR0
+ DDRPHY_DX2GCR0
+ DDRPHY_DX2GCR1
+ DDRPHY_DX2GCR2
+ DDRPHY_DX2GCR3
+ DDRPHY_DX2GCR4
+ DDRPHY_DX2GCR5
+ DDRPHY_DX2GSR0
+ DDRPHY_DX2GSR1
+ DDRPHY_DX2GSR2
+ DDRPHY_DX2GSR3
+ DDRPHY_DX2GSR4
+ DDRPHY_DX2GSR5
+ DDRPHY_DX2GSR6
+ DDRPHY_DX2GTR0
+ DDRPHY_DX3GCR0
+ DDRPHY_DX3GCR1
+ DDRPHY_DX3GCR2
+ DDRPHY_DX3GCR3
+ DDRPHY_DX3GCR4
+ DDRPHY_DX3GCR5
+ DDRPHY_DX3GSR0
+ DDRPHY_DX3GSR1
+ DDRPHY_DX3GSR2
+ DDRPHY_DX3GSR3
+ DDRPHY_DX3GSR4
+ DDRPHY_DX3GSR5
+ DDRPHY_DX3GSR6
+ DDRPHY_DX3GTR0
+ DDRPHY_DX4GCR0
+ DDRPHY_DX4GCR1
+ DDRPHY_DX4GCR2
+ DDRPHY_DX4GCR3
+ DDRPHY_DX4GCR4
+ DDRPHY_DX4GCR5
+ DDRPHY_DX4GSR0
+ DDRPHY_DX4GSR1
+ DDRPHY_DX4GSR2
+ DDRPHY_DX4GSR3
+ DDRPHY_DX4GSR4
+ DDRPHY_DX4GSR5
+ DDRPHY_DX4GSR6
+ DDRPHY_DX4GTR0
+ DDRPHY_DX8SL0DQSCTL
+ DDRPHY_DX8SL0DXCTL2
+ DDRPHY_DX8SL0IOCR
+ DDRPHY_DX8SL0PLLCR0
+ DDRPHY_DX8SL1DQSCTL
+ DDRPHY_DX8SL1DXCTL2
+ DDRPHY_DX8SL1IOCR
+ DDRPHY_DX8SL1PLLCR0
+ DDRPHY_DX8SL2DQSCTL
+ DDRPHY_DX8SL2DXCTL2
+ DDRPHY_DX8SL2IOCR
+ DDRPHY_DX8SL2PLLCR0
+ DDRPHY_DXCCR
+ DDRPHY_ODTCR
+ DDRPHY_PGCR0
+ DDRPHY_PGCR1
+ DDRPHY_PGCR2
+ DDRPHY_PGCR3
+ DDRPHY_PGCR5
+ DDRPHY_PGCR6
+ DDRPHY_PGSR0
+ >;
+
+ ti,phy-ctl = <
+ DDRPHY_DTCR0
+ DDRPHY_DTCR1
+ DDRPHY_MR0
+ DDRPHY_MR1
+ DDRPHY_MR2
+ DDRPHY_MR3
+ DDRPHY_MR4
+ DDRPHY_MR5
+ DDRPHY_MR6
+ DDRPHY_MR11
+ DDRPHY_MR12
+ DDRPHY_MR13
+ DDRPHY_MR14
+ DDRPHY_MR22
+ DDRPHY_PIR
+ DDRPHY_PLLCR0
+ DDRPHY_RANKIDR
+ DDRPHY_VTCR0
+ >;
+
+ ti,phy-ioctl = <
+ DDRPHY_ACIOCR5
+ DDRPHY_IOVCR0
+ >;
+
+ ti,phy-timing = <
+ DDRPHY_DTPR0
+ DDRPHY_DTPR1
+ DDRPHY_DTPR2
+ DDRPHY_DTPR3
+ DDRPHY_DTPR4
+ DDRPHY_DTPR5
+ DDRPHY_DTPR6
+ DDRPHY_PTR2
+ DDRPHY_PTR3
+ DDRPHY_PTR4
+ DDRPHY_PTR5
+ DDRPHY_PTR6
+ >;
+
+ ti,phy-zq = <
+ DDRPHY_ZQ0PR0
+ DDRPHY_ZQ1PR0
+ DDRPHY_ZQ2PR0
+ DDRPHY_ZQ3PR0
+ DDRPHY_ZQCR
+ >;
+ };
+};
diff --git a/arch/arm/dts/k3-am654-r5-base-board.dts
b/arch/arm/dts/k3-am654-r5-base-board.dts
new file mode 100644
index 0000000000..c1491d906d
--- /dev/null
+++ b/arch/arm/dts/k3-am654-r5-base-board.dts
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am654.dtsi"
+#include "k3-am654-base-board-u-boot.dtsi"
+#include "k3-am654-base-board-ddr4-1333MHz.dtsi"
+#include "k3-am654-ddr.dtsi"
+
+/ {
+ compatible = "ti,am654-evm", "ti,am654";
+ model = "Texas Instruments AM654 R5 Base Board";
+
+ aliases {
+ serial0 = &wkup_uart0;
+ serial2 = &main_uart0;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x0 0x00a90000 0x0 0x10>;
+ power-domains = <&k3_pds 61>,
+ <&k3_pds 202>;
+ resets = <&k3_reset 202 0>;
+ assigned-clocks = <&k3_clks 202 0>;
+ assigned-clock-rates = <800000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ vtt_supply: vtt_supply {
+ compatible = "regulator-gpio";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
+ states = <0 0x0 3300000 0x1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ timer1: timer@40400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x40400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <25000000>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&cbass_mcu {
+ mcu_secproxy: secproxy@28380000 {
+ compatible = "ti,am654-secure-proxy";
+ reg = <0x0 0x2a380000 0x0 0x80000>,
+ <0x0 0x2a400000 0x0 0x80000>,
+ <0x0 0x2a480000 0x0 0x80000>;
+ reg-names = "rt", "scfg", "target_data";
+ #mbox-cells = <1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_wakeup {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx";
+ u-boot,dm-spl;
+ };
+
+ wkup_gpio0: wkup_gpio0@42110000 {
+ compatible = "ti,k2g-gpio", "ti,keystone-gpio";
+ reg = <0x42110000 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ti,ngpio = <56>;
+ ti,davinci-gpio-unbanked = <0>;
+ clocks = <&k3_clks 59 0>;
+ clock-names = "gpio";
+ u-boot,dm-spl;
+ };
+
+};
+
+&dmsc {
+ mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
+ mbox-names = "tx", "rx", "notify";
+ ti,host-id = <4>;
+ ti,secure-host;
+};
+
+&wkup_uart0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_uart0_pins_default>;
+ status = "okay";
+};
+
+&wkup_pmx0 {
+ u-boot,dm-spl;
+ wkup_uart0_pins_default: wkup_uart0_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /*
(AB1) WKUP_UART0_RXD */
+ AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /*
(AB5) WKUP_UART0_TXD */
+ AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /*
(AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
+ AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /*
(AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
+ >;
+ u-boot,dm-spl;
+ };
+
+ wkup_vtt_pins_default: wkup_vtt_pins_default {
+ pinctrl-single,pins = <
+ AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7)
/* WKUP_GPIO0_28 */
+ >;
+ u-boot,dm-spl;
+ };
+};
+
+&memorycontroller {
+ vtt-supply = <&vtt_supply>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wkup_vtt_pins_default>;
+};
--
2.19.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
