On Thu, 2018-10-04 at 21:31 +0530, Jagan Teki wrote:
> On Tue, Oct 2, 2018 at 4:38 PM Ryder Lee <ryder....@mediatek.com> wrote:
> >
> > From: Guochun Mao <guochun....@mediatek.com>
> >
> > This patch adds MT7629 qspi driver for accessing SPI NOR flash.
> >
> > Cc: Jagan Teki <ja...@openedev.com>
> > Signed-off-by: Guochun Mao <guochun....@mediatek.com>
> > ---
> > drivers/spi/Kconfig | 7 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/mtk_qspi.c | 406
> > +++++++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 414 insertions(+)
> > create mode 100644 drivers/spi/mtk_qspi.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index 7d4d47d..0c37ac0 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -117,6 +117,13 @@ config MVEBU_A3700_SPI
> > used to access the SPI NOR flash on platforms embedding this
> > Marvell IP core.
> >
> > +config MTK_QSPI
> > + bool "Mediatek QSPI driver"
> > + help
> > + Enable the Mediatek QSPI driver. This driver can be
> > + used to access the SPI NOR flash on platforms embedding this
> > + Mediatek QSPI IP core.
> > +
> > config PIC32_SPI
> > bool "Microchip PIC32 SPI driver"
> > depends on MACH_PIC32
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index 6679987..f1c6400 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -32,6 +32,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
> > obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
> > obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> > obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
> > +obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o
> > obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o
> > obj-$(CONFIG_MXC_SPI) += mxc_spi.o
> > obj-$(CONFIG_MXS_SPI) += mxs_spi.o
> > diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c
> > new file mode 100644
> > index 0000000..87117fa
> > --- /dev/null
> > +++ b/drivers/spi/mtk_qspi.c
> > @@ -0,0 +1,406 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2018 MediaTek, Inc.
> > + * Author : guochun....@mediatek.com
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <malloc.h>
> > +#include <spi.h>
> > +#include <asm/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/ioport.h>
> > +
> > +/* Register Offset */
> > +struct mtk_qspi_regs {
> > + u32 cmd;
> > + u32 cnt;
> > + u32 rdsr;
> > + u32 rdata;
> > + u32 radr[3];
> > + u32 wdata;
> > + u32 prgdata[6];
> > + u32 shreg[10];
> > + u32 cfg[2];
> > + u32 shreg10;
> > + u32 mode_mon;
> > + u32 status[4];
> > + u32 flash_time;
> > + u32 flash_cfg;
> > + u32 reserved_0[3];
> > + u32 sf_time;
> > + u32 pp_dw_data;
> > + u32 reserved_1;
> > + u32 delsel_0[2];
> > + u32 intrstus;
> > + u32 intren;
> > + u32 reserved_2;
> > + u32 cfg3;
> > + u32 reserved_3;
> > + u32 chksum;
> > + u32 aaicmd;
> > + u32 wrprot;
> > + u32 radr3;
> > + u32 dual;
> > + u32 delsel_1[3];
> > +};
> > +
> > +struct mtk_qspi_platdata {
> > + fdt_addr_t reg_base;
> > + fdt_addr_t mem_base;
> > +};
> > +
> > +struct mtk_qspi_priv {
> > + struct mtk_qspi_regs *regs;
> > + unsigned long *mem_base;
> > + u8 op;
> > + /* Max paras length is 3 bytes. */
> > + u8 tx[3];
> > + u32 txlen;
> > + u8 *rx;
> > + u32 rxlen;
> > +};
> > +
> > +#define MTK_QSPI_CMD_POLLINGREG_US 500000
> > +#define MTK_QSPI_WRBUF_SIZE 256
> > +#define MTK_QSPI_COMMAND_ENABLE 0x30
> > +
> > +/* NOR flash controller commands */
> > +#define MTK_QSPI_RD_TRIGGER BIT(0)
> > +#define MTK_QSPI_READSTATUS BIT(1)
> > +#define MTK_QSPI_PRG_CMD BIT(2)
> > +#define MTK_QSPI_WR_TRIGGER BIT(4)
> > +#define MTK_QSPI_WRITESTATUS BIT(5)
> > +#define MTK_QSPI_AUTOINC BIT(7)
> > +
> > +/* NOR flash commands */
> > +#define MTK_QSPI_OP_WREN 0x6
> > +#define MTK_QSPI_OP_READ_QUAD 0x6B
> > +#define MTK_QSPI_OP_READ_DUAL 0x3B
> > +#define MTK_QSPI_OP_FAST_READ 0xB
> > +#define MTK_QSPI_OP_READ 0x3
> > +#define MTK_QSPI_OP_PP 0x2
>
> NAK, we don't allow flash commands in spi. Better handle via spi-mem
> or flash side.
OK, we'll write another version base spi-mem.
Thanks.
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