On Sat, Oct 06, 2018 at 11:23:32PM +0800, Icenowy Zheng wrote: > Currently the DRAM bus gate and reset is changed at the same time in > H6 DRAM initialization code, which disobeys the user manual's > programming guide. > > Fix the sequence by follow the sequence suggested by the user manual > (ungate the bus clock after release the reset signal). > > By some experiments it seems to fix the DRAM size detection failure that > rarely happens. > > Signed-off-by: Icenowy Zheng <icen...@aosc.io>
Acked-by: Maxime Ripard <maxime.rip...@bootlin.com> Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
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