[U-Boot] [PATCH v2 1/4] aspeed: ast2500: Add AHB clock

[Cédric Le Goater]

The AHB clock is used by the FMC/SPI controllers.

Signed-off-by: Cédric Le Goater <c...@kaod.org>
Reviewed-by: Joel Stanley <j...@jms.id.au>
---
 arch/arm/include/asm/arch-aspeed/scu_ast2500.h |  2 ++
 include/dt-bindings/clock/ast2500-scu.h        |  1 +
 drivers/clk/aspeed/clk_ast2500.c               | 12 ++++++++++++
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h 
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 4988ced7ddcc..6a90ded752ad 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -11,6 +11,8 @@
 #define SCU_HWSTRAP_VGAMEM_MASK                (3 << SCU_HWSTRAP_VGAMEM_SHIFT)
 #define SCU_HWSTRAP_MAC1_RGMII         (1 << 6)
 #define SCU_HWSTRAP_MAC2_RGMII         (1 << 7)
+#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT   9
+#define SCU_HWSTRAP_AXIAHB_DIV_MASK    (0x7 << SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
 #define SCU_HWSTRAP_DDR4               (1 << 24)
 #define SCU_HWSTRAP_CLKIN_25MHZ                (1 << 23)
 
diff --git a/include/dt-bindings/clock/ast2500-scu.h 
b/include/dt-bindings/clock/ast2500-scu.h
index 4803abe9f628..03e6d16d3de0 100644
--- a/include/dt-bindings/clock/ast2500-scu.h
+++ b/include/dt-bindings/clock/ast2500-scu.h
@@ -17,6 +17,7 @@
 #define BCLK_MACCLK    103
 #define BCLK_SDCLK     104
 #define BCLK_ARMCLK    105
+#define BCLK_HCLK      106
 
 #define MCLK_DDR       201
 
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 526470051c5d..c55f8d5ae30d 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -143,6 +143,18 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
                        rate = rate / apb_div;
                }
                break;
+       case BCLK_HCLK:
+               {
+                       ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap)
+                                             & SCU_HWSTRAP_AXIAHB_DIV_MASK)
+                                            >> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
+                       ulong axi_div = 2;
+
+                       rate = ast2500_get_hpll_rate(
+                               clkin, readl(&priv->scu->h_pll_param));
+                       rate = rate / axi_div / ahb_div;
+               }
+               break;
        case PCLK_UART1:
                rate = ast2500_get_uart_clk_rate(priv->scu, 1);
                break;
-- 
2.17.1

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