Change the dms-ba16 configurations to support both Q7 Dual/Quad and DualLite
modules
Add the DDR3L parameters support for the DualLite
Signed-off-by: Ken Lin <yungching0...@gmail.com>
---
arch/arm/mach-imx/mx6/Kconfig | 1 -
board/advantech/dms-ba16/Kconfig | 7 +++
board/advantech/dms-ba16/ddr-setup-dl.cfg | 39 ++++++++++++++
board/advantech/dms-ba16/dms-ba16_2g_dl.cfg | 23 ++++++++
board/advantech/dms-ba16/samsung-2g-dl.cfg | 58 +++++++++++++++++++++
configs/dms-ba16-2g-dl_defconfig | 54 +++++++++++++++++++
6 files changed, 181 insertions(+), 1 deletion(-)
create mode 100644 board/advantech/dms-ba16/ddr-setup-dl.cfg
create mode 100644 board/advantech/dms-ba16/dms-ba16_2g_dl.cfg
create mode 100644 board/advantech/dms-ba16/samsung-2g-dl.cfg
create mode 100644 configs/dms-ba16-2g-dl_defconfig
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index a2799c436e..e3784d00fa 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -102,7 +102,6 @@ choice
config TARGET_ADVANTECH_DMS_BA16
bool "Advantech dms-ba16"
select BOARD_LATE_INIT
- select MX6Q
imply CMD_SATA
config TARGET_APALIS_IMX6
diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig
index f5d9f61f13..c61fbabb31 100644
--- a/board/advantech/dms-ba16/Kconfig
+++ b/board/advantech/dms-ba16/Kconfig
@@ -6,13 +6,20 @@ choice
config SYS_DDR_1G
bool "1GiB"
+ select MX6Q
config SYS_DDR_2G
bool "2GiB"
+ select MX6Q
+
+config SYS_DDR3L_2G
+ bool "2GiB"
+ select MX6DL
endchoice
config IMX_CONFIG
+ default "board/advantech/dms-ba16/dms-ba16_2g_dl.cfg" if SYS_DDR3L_2G
default "board/advantech/dms-ba16/dms-ba16_2g.cfg" if SYS_DDR_2G
default "board/advantech/dms-ba16/dms-ba16_1g.cfg" if SYS_DDR_1G
diff --git a/board/advantech/dms-ba16/ddr-setup-dl.cfg
b/board/advantech/dms-ba16/ddr-setup-dl.cfg
new file mode 100644
index 0000000000..7f567c3f12
--- /dev/null
+++ b/board/advantech/dms-ba16/ddr-setup-dl.cfg
@@ -0,0 +1,39 @@
+/* DDR IO */
+DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
+DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
+DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
+DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
+DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
+DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
+DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
+DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
+DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
+DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000028
+DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000028
+DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
+DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B4DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B5DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B6DS, 0x00000028
+DATA 4, MX6_IOM_GRP_B7DS, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM4, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM5, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM6, 0x00000028
+DATA 4, MX6_IOM_DRAM_DQM7, 0x00000028
diff --git a/board/advantech/dms-ba16/dms-ba16_2g_dl.cfg
b/board/advantech/dms-ba16/dms-ba16_2g_dl.cfg
new file mode 100644
index 0000000000..6d09cd55f7
--- /dev/null
+++ b/board/advantech/dms-ba16/dms-ba16_2g_dl.cfg
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *
+ * Copyright 2018 Advantech Corporation.
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+IMAGE_VERSION 2
+BOOT_FROM sd
+
+#define __ASSEMBLY__
+#include <config.h>
+#include "asm/arch/mx6-ddr.h"
+#include "asm/arch/iomux.h"
+#include "asm/arch/crm_regs.h"
+
+#include "ddr-setup-dl.cfg"
+#include "samsung-2g-dl.cfg"
+#include "clocks.cfg"
diff --git a/board/advantech/dms-ba16/samsung-2g-dl.cfg
b/board/advantech/dms-ba16/samsung-2g-dl.cfg
new file mode 100644
index 0000000000..280e9f01a3
--- /dev/null
+++ b/board/advantech/dms-ba16/samsung-2g-dl.cfg
@@ -0,0 +1,58 @@
+/* Calibrations */
+/* ZQ */
+DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
+/* write leveling */
+DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x004B004E
+DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003F003E
+DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00230026
+DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0030
+/* Read DQS Gating calibration */
+DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x423C0238
+DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02280230
+DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x421C0220
+DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x02080220
+/* Read calibration */
+DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x40444846
+DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x46464A3E
+/* Write calibration */
+DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36383234
+DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x38383A32
+/* read data bit delay */
+DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
+DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
+
+/* Complete calibration by forced measurment */
+DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
+DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
+
+/* MMDC init */
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
+DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
+DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
+DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
+DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
+DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
+DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
+DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
+DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
+DATA 4, MX6_MMDC_P0_MDCTL, 0x841a0000
+
+/* Initialize memory */
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
+DATA 4, MX6_MMDC_P0_MDSCR, 0x13208030
+DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
+DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
+DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
+DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
+DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
+DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
diff --git a/configs/dms-ba16-2g-dl_defconfig b/configs/dms-ba16-2g-dl_defconfig
new file mode 100644
index 0000000000..256e774205
--- /dev/null
+++ b/configs/dms-ba16-2g-dl_defconfig
@@ -0,0 +1,54 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_SYS_TEXT_BASE=0x17800000
+CONFIG_TARGET_ADVANTECH_DMS_BA16=y
+CONFIG_SYS_DDR3L_2G=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_BOOTDELAY=1
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
+CONFIG_SUPPORT_RAW_INITRD=y
+CONFIG_DEFAULT_FDT_FILE="imx6dl-dms-ba16.dtb"
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_DWC_AHSATA=y
+CONFIG_FSL_ESDHC=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_PHYLIB=y
+CONFIG_MII=y
+CONFIG_SPI=y
+CONFIG_MXC_SPI=y
+CONFIG_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Advantech"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_VIDEO=y
+# CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_OF_LIBFDT=y
--
2.17.1
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