Add CLK and RESET support for sun8i_emac driver to
enable TX clock and reset pins via CLK and RESET
framework.
Cc: Joe Hershberger <joe.hershber...@ni.com>
Cc: Lothar Felten <lothar.fel...@gmail.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/net/sun8i_emac.c | 56 ++++++++++++++++++++++++++++------------
1 file changed, 40 insertions(+), 16 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 5ee4c2f993..ad2d390f4e 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -10,6 +10,7 @@
*
*/
+#include <clk.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
@@ -20,6 +21,7 @@
#include <malloc.h>
#include <miiphy.h>
#include <net.h>
+#include <reset.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>
#ifdef CONFIG_DM_GPIO
#include <asm-generic/gpio.h>
@@ -131,6 +133,8 @@ struct emac_eth_dev {
phys_addr_t sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
+ struct clk tx_clk;
+ struct reset_ctl tx_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
@@ -632,9 +636,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
}
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int ret;
+
+ ret = clk_enable(&priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable TX clock\n");
+ return ret;
+ }
+
+ if (reset_valid(&priv->tx_rst)) {
+ ret = reset_deassert(&priv->tx_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert TX reset\n");
+ return ret;
+ }
+ }
if (priv->variant == H3_EMAC) {
/* Only H3/H5 have clock controls for internal EPHY */
@@ -649,19 +668,7 @@ static void sun8i_emac_board_setup(struct emac_eth_dev
*priv)
}
}
- if (priv->variant == R40_GMAC) {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
- } else {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
- }
+ return 0;
}
#if defined(CONFIG_DM_GPIO)
@@ -787,10 +794,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->mac_reg = (void *)pdata->iobase;
- sun8i_emac_board_setup(priv);
+ ret = sun8i_emac_board_setup(priv);
+ if (ret)
+ return ret;
+
sun8i_emac_set_syscon(priv);
sun8i_mdio_init(dev->name, dev);
@@ -819,8 +830,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice
*dev)
int offset = 0;
#ifdef CONFIG_DM_GPIO
int reset_flags = GPIOD_IS_OUT;
- int ret = 0;
#endif
+ int ret;
pdata->iobase = devfdt_get_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
@@ -835,6 +846,19 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct
udevice *dev)
return -EINVAL;
}
+ ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to get TX clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name_optional(dev, "stmmaceth",
+ &priv->tx_rst, true);
+ if (ret) {
+ dev_err(dev, "failed to get TX reset\n");
+ return ret;
+ }
+
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
if (offset < 0) {
debug("%s: cannot find syscon node\n", __func__);
--
2.18.0.321.gffc6fa0e3
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