EPHY CLK and RESET is availble in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respetive
clock and reset reg and bits.
Cc: Joe Hershberger <joe.hershber...@ni.com>
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
drivers/clk/sunxi/clk_h3.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 88086580f4..3d5dc2cbed 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -34,6 +34,8 @@ static struct ccu_clk_map h3_clks[] = {
[CLK_BUS_UART2] = { 0x06c, BIT(18), NULL },
[CLK_BUS_UART3] = { 0x06c, BIT(19), NULL },
+ [CLK_BUS_EPHY] = { 0x070, BIT(0), NULL },
+
[CLK_MMC0] = { 0x088, BIT(31), &mmc_clk_set_rate },
[CLK_MMC1] = { 0x08c, BIT(31), &mmc_clk_set_rate },
[CLK_MMC2] = { 0x090, BIT(31), &mmc_clk_set_rate },
@@ -73,6 +75,8 @@ static struct ccu_reset_map h3_resets[] = {
[RST_BUS_OHCI2] = { 0x2c0, BIT(30) },
[RST_BUS_OHCI3] = { 0x2c0, BIT(31) },
+ [RST_BUS_EPHY] = { 0x2c8, BIT(2) },
+
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
--
2.18.0.321.gffc6fa0e3
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