Am Fr., 10. Aug. 2018 um 11:39 Uhr schrieb Bin Meng <bmeng...@gmail.com>:
>
> It was observed sometimes U-Boot as the coreboot payload fails to
> boot on QEMU. This is because TSC calibration fails with no valid
> frequency. This adds default TSC frequency in the device tree.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmei...@gmail.com>
> ---
>
> arch/x86/dts/coreboot.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/x86/dts/coreboot.dts b/arch/x86/dts/coreboot.dts
> index a94f781..e212f3d 100644
> --- a/arch/x86/dts/coreboot.dts
> +++ b/arch/x86/dts/coreboot.dts
> @@ -30,6 +30,10 @@
> stdout-path = "/serial";
> };
>
> + tsc-timer {
> + clock-frequency = <1000000000>;
> + };
> +
> pci {
> compatible = "pci-x86";
> u-boot,dm-pre-reloc;
> --
> 2.7.4
>
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--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info
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