On 30.07.2018 16:04, Marek Vasut wrote:
On 07/30/2018 04:03 PM, Simon Goldschmidt wrote:
On 12.05.2018 22:28, Marek Vasut wrote:
Pull the serial port configuration from DT and use DM serial instead
of having the serial configuration in two places, DT and board config.
Signed-off-by: Marek Vasut <ma...@denx.de>
Cc: Chin Liang See <chin.liang....@intel.com>
Cc: Dinh Nguyen <dingu...@kernel.org>
---
arch/arm/Kconfig | 3 +++
arch/arm/dts/socfpga.dtsi | 2 ++
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 1 +
include/configs/socfpga_common.h | 8 --------
4 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 532aa41a87..2012ac6410 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -737,6 +737,7 @@ config ARCH_SOCFPGA
select ARCH_MISC_INIT
select CPU_V7A
select DM
+ select DM_SERIAL
select ENABLE_ARM_SOC_BOOT0_HOOK
select OF_CONTROL
select SPL_LIBCOMMON_SUPPORT
@@ -746,11 +747,13 @@ config ARCH_SOCFPGA
select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL
select SPL_SERIAL_SUPPORT
+ select SPL_DM_SERIAL
select SPL_SPI_FLASH_SUPPORT if SPL_SPI_SUPPORT
select SPL_SPI_SUPPORT if DM_SPI
select SPL_WATCHDOG_SUPPORT
select SUPPORT_SPL
select SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
+ select SYS_NS16550
select SYS_THUMB_BUILD
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index e64127fcb2..314449478d 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -737,6 +737,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
+ clock-frequency = <100000000>;
};
uart1: serial1@ffc03000 {
@@ -746,6 +747,7 @@
reg-shift = <2>;
reg-io-width = <4>;
clocks = <&l4_sp_clk>;
+ clock-frequency = <100000000>;
};
rst: rstmgr@ffd05000 {
diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
index b573d0e658..06b61cb0af 100644
--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
+++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
@@ -24,6 +24,7 @@
};
&uart1 {
+ clock-frequency = <50000000>;
u-boot,dm-pre-reloc;
status = "okay";
};
diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h
index 54b9edc97c..a60da85499 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -173,14 +173,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
* Serial Driver
*/
#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS
-#define CONFIG_SYS_NS16550_CLK 100000000
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS
-#define CONFIG_SYS_NS16550_CLK 50000000
-#endif
/*
* USB
Unfortunately I saw this just now, but it seems this breaks GEN5 SPL? At
least git-bisect told me that 73172753f4f3351ed1c9d2f6586fc599ce4e728c
is the first bad commit.
I tested socfpga_socrates_defconfig on my socrates board.
Any idea what's wrong there?
Nope, this should work fine. Can you investigate ?
Ok, so after adding "u-boot,dm-pre-reloc" to uart0 in
socfpga_cyclone5_socrates.dts, U-Boot works (combined with an old SPL).
SPL still does not work. Any idea? How does SPL get the uart?
Thanks for any pointers.
Simon
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