On 06/23/2018 05:55 AM, Marek Vasut wrote: > On 06/06/2018 08:47 PM, Marek Vasut wrote: >> On 05/31/2018 12:00 PM, Marek Vasut wrote: >>> On 05/31/2018 11:52 AM, See, Chin Liang wrote: >>>> On Tue, 2018-05-29 at 18:39 +0200, Marek Vasut wrote: >>>>> Make sure the ARM ACTLR register has correct configuration, otherwise >>>>> the Linux kernel refuses to boot. In particular, the "Write Full Line >>>>> of Zeroes" bit must be cleared. >>>>> >>>>> Signed-off-by: Marek Vasut <ma...@denx.de> >>>>> Cc: Chin Liang See <chin.liang....@intel.com> >>>>> Cc: Dinh Nguyen <dingu...@kernel.org> >>>>> --- >>>>> NOTE: This gem was well hidden in the Altera U-Boot fork and is >>>>> really needed. >>>>> What is not entirely clear to me is WHY ? So why is this needed >>>>> ? >>>> >>>> I vaguely recall it's related to HW constrain. And check back the >>>> downstream U-Boot, actually we need to set the bit instead clearing >>>> it. https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2 >>>> 014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/pl310.c >>> >>> You are clearing it here: >>> https://github.com/altera-opensource/u-boot-socfpga/blob/socfpga_v2014.10_arria10_bringup/arch/arm/cpu/armv7/socfpga_arria10/lowlevel_init.S#L35 >>> >>> The PL310 configuration is a different register. What HW constraint ? >>> I'd really like to understand this problem. >> >> Bump ? I had a report the register even has to be set to 0 , otherwise >> there are ethernet problems. What is going on with this register ? > > Bump again ? >
Expanding the CC list. I am tempted to stop accepting any socfpga patches until this is resolved. -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
