I would not be surprised to see JFFS2 problems with most i.MX platforms. The nand ecc includes the spare area so you can not write a JFFS2 free marker to spare and then later write to the main area. There are patches for JFFS2 in the kernel for this. I don't know about u-boot.
John On Mon, Feb 15, 2010 at 11:15 AM, Andreas Orfanos <aorfa...@airvana.com> wrote: > Hi, > > Finally managed to boot uboot from NAND. MX51_3STACK u-boot was crashing > somewhere in the beginning. There, board_init() was calling > setup_core_voltages() and there a write to clock registers was making u-boot > to crash. > I removed that write and thing booted fine. I will make a patch with all the > changes and post it here. > > However, JFFS2 it seems quite slow, very slow... I have setup some mtdparts, > one of them "mnt", and then make a "chpart nand.mnt". When I try a list > command "ls", the whole listing is incredibly slow. > > Does anyone ever seen issues NAND and Jff2 on MX51? Any u-boot version that > you have seen it working? > > Any advice will be very much appreciated. > > Regards, > Andreas > > > -----Original Message----- > From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de] On > Behalf Of Andreas Orfanos > Sent: 11 February 2010 10:25 > To: Eric Bénard > Cc: U-Boot user list > Subject: Re: [U-Boot] Booting from NAND on MX51 > > Hi Eric, > > Thank you for the information. Yes, I have found 2 DCD errors when comparing > RedBood DCDs with u-boot DCDs, > I fixed those error and now the MX51 ROM boot loader copies the u-boot code > into RAM. > Someone will need to double check those in Redboot with those in u-boot and > update the u-boot code. > See below the flash_header.S file that I am using. > > Now the system copies code from NAND but crashes somewhere at the early stage. > Are any more switches that might need to be turned "on", or "off" in the > mx51_3stack config file? > > Regards, > Andreas > > > /* > * Copyright 2009 Freescale Semiconductor, Inc. > * > * This program is free software; you can redistribute it and/or > * modify it under the terms of the GNU General Public License as > * published by the Free Software Foundation; either version 2 of > * the License, or (at your option) any later version. > * > * This program is distributed in the hope that it will be useful, > * but WITHOUT ANY WARRANTY; without even the implied warranty of > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > * > * You should have received a copy of the GNU General Public License > * along with this program; if not, write to the Free Software > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > * MA 02111-1307 USA > */ > > #include <config.h> > #include <asm/arch/mx51.h> > #include "board-mx51_3stack.h" > > #ifdef CONFIG_FLASH_HEADER > #ifndef CONFIG_FLASH_HEADER_OFFSET > # error "Must define the offset of flash header" > #endif > #define MXC_DCD_ITEM(i, type, addr, val) \ > dcd_node_##i: \ > .word type ; \ > .word addr ; \ > .word val ; \ > > .section ".text.flasheader", "x" > b _start > .org CONFIG_FLASH_HEADER_OFFSET > app_code_jump_v: .word _start > app_code_code_barker: .word CONFIG_FLASH_HEADER_BARKER > app_code_csf: .word (TEXT_BASE + 0x40000 - 0x1000) //0 > dcd_ptr_ptr: .word dcd_ptr > super_root_key: .word 0 > dcd_ptr: .word dcd_array_start > app_dest_ptr: .word TEXT_BASE > dcd_array_start: > magic: .word 0xB17219E9 > dcd_array_size: .word dcd_data_end - dcd_array_start - 8 > /* DCD */ > /* DDR2 IOMUX configuration */ > MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200) > MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x50c, 0x20c5) > MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x510, 0x20c5) > MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x83c, 0x2) > MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x848, 0x2) > MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4b8, 0xe7) > MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x45) > MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x45) > MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x45) > MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x45) > MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x820, 0x0) > MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x4a4, 0x3) > MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x4a8, 0x3) > MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x4ac, 0xe3) > MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3) > MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3) > MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3) > MXC_DCD_ITEM(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2) > /* Set drive strength to MAX */ > #if 0 > MXC_DCD_ITEM(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6) > MXC_DCD_ITEM(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6) > MXC_DCD_ITEM(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6) > MXC_DCD_ITEM(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6) > #endif > /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */ > /* CAS=3, BL=4 */ > MXC_DCD_ITEM(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000) > MXC_DCD_ITEM(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000) > MXC_DCD_ITEM(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0) > MXC_DCD_ITEM(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa) > MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa) > /* Init DRAM on CS0 */ > MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) > MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a) > MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b) > MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019) /* error*/ > MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018) > MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) > MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) > MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) > MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018) > MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019) > MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019) /* error */ > MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) > /* Init DRAM on CS1 */ > MXC_DCD_ITEM(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) > MXC_DCD_ITEM(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e) > MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f) > MXC_DCD_ITEM(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d) > MXC_DCD_ITEM(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c) > MXC_DCD_ITEM(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) > MXC_DCD_ITEM(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) > MXC_DCD_ITEM(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) > MXC_DCD_ITEM(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c) > MXC_DCD_ITEM(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d) > MXC_DCD_ITEM(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d) > MXC_DCD_ITEM(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) > MXC_DCD_ITEM(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000) > MXC_DCD_ITEM(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000) > MXC_DCD_ITEM(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0) > MXC_DCD_ITEM(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000) > MXC_DCD_ITEM(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) > > MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000) > MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000) > MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000) > MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000) > MXC_DCD_ITEM(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000) > > dcd_data_end: > //image_len: .word 0x80000 > image_len: .word __u_boot_cmd_end - TEXT_BASE > #endif > > > > > -----Original Message----- > From: Eric Bénard [mailto:e...@eukrea.com] > Sent: 10 February 2010 15:16 > To: Andreas Orfanos > Cc: U-Boot user list > Subject: Re: [U-Boot] Booting from NAND on MX51 > > Hi Andreas, > > Le 10/02/2010 15:55, Andreas Orfanos a écrit : >> Did you have to make changes in cpu/arm_cortex8/start.S file? > we are using u-boot-2009.01 + freescale patches. > No change to start.S (except a small hack to turn on a led to check > u-boot is properly loaded and run). > >> I don't have to make any changes on DCD table anyway, as it has already >> produced by freescale for mx51_3stack board >> > I started with the DCD of Redboot for 3Stack as the one for the 3Stack > in u-boot never worked here. > If you don't manage to get it running using RedBoot DCD, come back to me > on next thursday where I should be able to extract some patches as I'm > actually busy on an other subject. > > Eric > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
