Tom wrote:
>> #ifdef CONFIG_SYS_NAND_DBW_16
>> - AT91_SMC_DBW_16 |
>> + AT91_SMC_MODE_DBW_16 |
>
> Name of define should not change
> apply globally
Some flag names are not refer to hw register (e.g.AT91_SMC_DBW_16).
In this case defines with new name are added with c structure.
Only this names are changed by soc access updates.
>> #ifdef CONFIG_MACB
>> static void at91sam9263ek_macb_hw_init(void)
>> {
>> - unsigned long rstc;
>> -
>> + unsigned long erstl;
>
> Keep name of the variable the same
>
>> + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
>> + at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
>> + at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE;
>> /* Enable clock */
>> - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
>> + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
>>
>> /*
>> * Disable pull-up on:
>> @@ -104,35 +112,27 @@ static void at91sam9263ek_macb_hw_init(void)
>> *
>> * PHY has internal pull-down
>> */
>> - writel(pin_to_mask(AT91_PIN_PC25),
>> - pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
>> - writel(pin_to_mask(AT91_PIN_PE25) |
>> - pin_to_mask(AT91_PIN_PE26),
>> - pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
>>
>> - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
>> + writel(AT91_PIN_TO_MASK(25), &pio->pioc.pudr);
>> + writel(AT91_PIN_TO_MASK(25) | AT91_PIN_TO_MASK(26), &pio->pioe.pudr);
>>
>> - /* Need to reset PHY -> 500ms reset */
>> - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
>> - (AT91_RSTC_ERSTL & (0x0D << 8)) |
>> - AT91_RSTC_URSTEN);
>> + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
>
> Name of define changes here.
> Do not do this..
> Revert names globally
rstc is a short for reset controller, so rstc should point to the hw registers.
erstl means external reset length. this patch do not change names, but it is
possible it use similar names by an other way.
>
>>
>>
>> @@ -151,39 +149,36 @@
>> #ifndef CONFIG_SKIP_LOWLEVEL_INIT
>> #define MASTER_PLL_MUL 171
>> #define MASTER_PLL_DIV 14
>> +#define MASTER_PLL_OUT 3
>>
>> /* clocks */
>> #define CONFIG_SYS_MOR_VAL \
>> - (AT91_PMC_MOSCEN | \
>> - (255 << 8)) /* Main Oscillator Start-up Time */
>> -#define CONFIG_SYS_PLLAR_VAL
>> \
>> - (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \
>> - AT91_PMC_OUT | \
>> - AT91_PMC_PLLCOUNT | /* PLL Counter */ \
>> - (2 << 28) | /* PLL Clock Frequency Range */ \
>> - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
>> + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
>> +#define CONFIG_SYS_PLLAR_VAL \
>> + (AT91_PMC_PLLAR_29 | \
>> + AT91_PMC_PLLxR_OUT(MASTER_PLL_OUT) | \
>> + AT91_PMC_PLLxR_PLLCOUNT(63) | \
>> + AT91_PMC_PLLxR_MUL(MASTER_PLL_MUL - 1) | \
>> + AT91_PMC_PLLxR_DIV(MASTER_PLL_DIV))
>>
>
> Why did this macro need to change ?
> Other macros are similar.
> If there isn't a change in the way registers are read/write,
> the macros should be the same.
See above.
Additional some defines are not correct, but work (see datashee)
eg.
The value of AT91_PMC_OUT and AT91_PMC_PLL value should not be fix.
The soc update will be change this.
regards Jens
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