Enable all types of non-secure access to PFE block registers.
Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlm...@nxp.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
---
Changes in v3: None
Changes in v2:
-Improved commit message to provide more description
arch/arm/include/asm/arch-fsl-layerscape/ns_access.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
index f46f1d8..fe97a93 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
@@ -26,6 +26,7 @@ enum csu_cslx_ind {
CSU_CSLX_PCIE3_IO,
CSU_CSLX_USB3 = 20,
CSU_CSLX_USB2,
+ CSU_CSLX_PFE = 23,
CSU_CSLX_SERDES = 32,
CSU_CSLX_QDMA,
CSU_CSLX_LPUART2,
@@ -105,6 +106,7 @@ static struct csu_ns_dev ns_dev[] = {
{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
{CSU_CSLX_USB3, CSU_ALL_RW},
{CSU_CSLX_USB2, CSU_ALL_RW},
+ {CSU_CSLX_PFE, CSU_ALL_RW},
{CSU_CSLX_SERDES, CSU_ALL_RW},
{CSU_CSLX_QDMA, CSU_ALL_RW},
{CSU_CSLX_LPUART2, CSU_ALL_RW},
--
2.7.4
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
