* convert all files cpu/../at91 to use at91_gpio driver syntax
* change AT91_PINP([A-F])(\d+) to AT91_PORTPIN(\1, \2),
this makes all 160 AT91_PINPxxx defines obsolete
* AT91_PINPxxx defines can be remove if all boards converted
to new SoC access
Signed-off-by: Jens Scharsig <js_at...@scharsoft.de>
---
cpu/arm926ejs/at91/at91cap9_devices.c | 100 +++++++++++++-------------
cpu/arm926ejs/at91/at91sam9260_devices.c | 100 +++++++++++++-------------
cpu/arm926ejs/at91/at91sam9261_devices.c | 60 ++++++++--------
cpu/arm926ejs/at91/at91sam9263_devices.c | 104 +++++++++++++-------------
cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 96 ++++++++++++------------
cpu/arm926ejs/at91/at91sam9rl_devices.c | 38 +++++-----
6 files changed, 249 insertions(+), 249 deletions(-)
diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c
b/cpu/arm926ejs/at91/at91cap9_devices.c
index 39e405f..c41e139 100644
--- a/cpu/arm926ejs/at91/at91cap9_devices.c
+++ b/cpu/arm926ejs/at91/at91cap9_devices.c
@@ -34,29 +34,29 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 22), 1); /* TXD0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 23), 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
+ at91_set_a_periph(AT91_PORTPIN(D, 0), 1); /* TXD1 */
+ at91_set_a_periph(AT91_PORTPIN(D, 1), 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
+ at91_set_a_periph(AT91_PORTPIN(D, 2), 1); /* TXD2 */
+ at91_set_a_periph(AT91_PORTPIN(D, 3), 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
+ at91_set_a_periph(AT91_PORTPIN(C, 30), 0); /* DRXD */
+ at91_set_a_periph(AT91_PORTPIN(C, 31), 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
}
@@ -82,71 +82,71 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_set_b_periph(AT91_PORTPIN(A, 0), 0); /* SPI0_MISO */
+ at91_set_b_periph(AT91_PORTPIN(A, 1), 0); /* SPI0_MOSI */
+ at91_set_b_periph(AT91_PORTPIN(A, 2), 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI0);
if (cs_mask & (1 << 0)) {
- at91_set_B_periph(AT91_PIN_PA5, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 5), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PA3, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PD0, 1);
+ at91_set_b_periph(AT91_PORTPIN(D, 0), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PD1, 1);
+ at91_set_b_periph(AT91_PORTPIN(D, 1), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA5, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 5), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PD0, 1);
+ at91_set_gpio_output(AT91_PORTPIN(D, 0), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD1, 1);
+ at91_set_gpio_output(AT91_PORTPIN(D, 1), 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(B, 12), 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PORTPIN(B, 13), 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(B, 14), 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_SPI1);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB15, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 15), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_A_periph(AT91_PIN_PB16, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 16), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PB17, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 17), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PB18, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 18), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB15, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 15), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB16, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 16), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PB17, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 17), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PB18, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 18), 1);
}
}
@@ -155,26 +155,26 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB21, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PB22, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PB25, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PB26, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PB27, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PB28, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PB23, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PB24, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PB30, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PB29, 0); /* EMDC */
+ at91_set_a_periph(AT91_PORTPIN(B, 21), 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PORTPIN(B, 22), 0); /* ERXDV */
+ at91_set_a_periph(AT91_PORTPIN(B, 25), 0); /* ERX0 */
+ at91_set_a_periph(AT91_PORTPIN(B, 26), 0); /* ERX1 */
+ at91_set_a_periph(AT91_PORTPIN(B, 27), 0); /* ERXER */
+ at91_set_a_periph(AT91_PORTPIN(B, 28), 0); /* ETXEN */
+ at91_set_a_periph(AT91_PORTPIN(B, 23), 0); /* ETX0 */
+ at91_set_a_periph(AT91_PORTPIN(B, 24), 0); /* ETX1 */
+ at91_set_a_periph(AT91_PORTPIN(B, 30), 0); /* EMDIO */
+ at91_set_a_periph(AT91_PORTPIN(B, 29), 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PC25, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
- at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
- at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
+ at91_set_b_periph(AT91_PORTPIN(C, 25), 0); /* ECRS */
+ at91_set_b_periph(AT91_PORTPIN(C, 26), 0); /* ECOL */
+ at91_set_b_periph(AT91_PORTPIN(C, 22), 0); /* ERX2 */
+ at91_set_b_periph(AT91_PORTPIN(C, 23), 0); /* ERX3 */
+ at91_set_b_periph(AT91_PORTPIN(C, 27), 0); /* ERXCK */
+ at91_set_b_periph(AT91_PORTPIN(C, 20), 0); /* ETX2 */
+ at91_set_b_periph(AT91_PORTPIN(C, 21), 0); /* ETX3 */
+ at91_set_b_periph(AT91_PORTPIN(C, 24), 0); /* ETXER */
#endif
}
#endif
@@ -182,8 +182,8 @@ void at91_macb_hw_init(void)
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */
- at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */
+ at91_set_a_periph(AT91_PORTPIN(A, 12), 0); /* CAN_TX */
+ at91_set_a_periph(AT91_PORTPIN(A, 13), 1); /* CAN_RX */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN);
diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c
b/cpu/arm926ejs/at91/at91sam9260_devices.c
index f86cb99..d7d6f49 100644
--- a/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -30,29 +30,29 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
+ at91_set_A_periph(AT91_PORTPIN(B, 4), 1); /* TXD0 */
+ at91_set_A_periph(AT91_PORTPIN(B, 5), 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
+ at91_set_A_periph(AT91_PORTPIN(B, 6), 1); /* TXD1 */
+ at91_set_A_periph(AT91_PORTPIN(B, 7), 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
+ at91_set_A_periph(AT91_PORTPIN(B, 8), 1); /* TXD2 */
+ at91_set_A_periph(AT91_PORTPIN(B, 9), 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
+ at91_set_A_periph(AT91_PORTPIN(B, 14), 0); /* DRXD */
+ at91_set_A_periph(AT91_PORTPIN(B, 15), 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
}
@@ -78,71 +78,71 @@ void at91_serial_hw_init(void)
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_set_A_periph(AT91_PORTPIN(A, 0), 0); /* SPI0_MISO */
+ at91_set_A_periph(AT91_PORTPIN(A, 1), 0); /* SPI0_MOSI */
+ at91_set_A_periph(AT91_PORTPIN(A, 2), 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PA3, 1);
+ at91_set_A_periph(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PC11, 1);
+ at91_set_B_periph(AT91_PORTPIN(C, 11), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PC16, 1);
+ at91_set_B_periph(AT91_PORTPIN(C, 16), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PC17, 1);
+ at91_set_B_periph(AT91_PORTPIN(C, 17), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PC11, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 11), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PC16, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 16), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PC17, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 17), 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
+ at91_set_A_periph(AT91_PORTPIN(B, 0), 0); /* SPI1_MISO */
+ at91_set_A_periph(AT91_PORTPIN(B, 1), 0); /* SPI1_MOSI */
+ at91_set_A_periph(AT91_PORTPIN(B, 2), 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI1);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB3, 1);
+ at91_set_A_periph(AT91_PORTPIN(B, 3), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PC5, 1);
+ at91_set_B_periph(AT91_PORTPIN(C, 5), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PC4, 1);
+ at91_set_B_periph(AT91_PORTPIN(C, 4), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_gpio_output(AT91_PIN_PC3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 3), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 3), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PC5, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 5), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PC4, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 4), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PC3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(C, 3), 1);
}
}
#endif
@@ -150,35 +150,35 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
+ at91_set_A_periph(AT91_PORTPIN(A, 19), 0); /* ETXCK_EREFCK */
+ at91_set_A_periph(AT91_PORTPIN(A, 17), 0); /* ERXDV */
+ at91_set_A_periph(AT91_PORTPIN(A, 14), 0); /* ERX0 */
+ at91_set_A_periph(AT91_PORTPIN(A, 15), 0); /* ERX1 */
+ at91_set_A_periph(AT91_PORTPIN(A, 18), 0); /* ERXER */
+ at91_set_A_periph(AT91_PORTPIN(A, 16), 0); /* ETXEN */
+ at91_set_A_periph(AT91_PORTPIN(A, 12), 0); /* ETX0 */
+ at91_set_A_periph(AT91_PORTPIN(A, 13), 0); /* ETX1 */
+ at91_set_A_periph(AT91_PORTPIN(A, 21), 0); /* EMDIO */
+ at91_set_A_periph(AT91_PORTPIN(A, 20), 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
+ at91_set_B_periph(AT91_PORTPIN(A, 28), 0); /* ECRS */
+ at91_set_B_periph(AT91_PORTPIN(A, 29), 0); /* ECOL */
+ at91_set_B_periph(AT91_PORTPIN(A, 25), 0); /* ERX2 */
+ at91_set_B_periph(AT91_PORTPIN(A, 26), 0); /* ERX3 */
+ at91_set_B_periph(AT91_PORTPIN(A, 27), 0); /* ERXCK */
#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260)
/*
* use PA10, PA11 for ETX2, ETX3.
* PA23 and PA24 are for TWI EEPROM
*/
- at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
+ at91_set_B_periph(AT91_PORTPIN(A, 10), 0); /* ETX2 */
+ at91_set_B_periph(AT91_PORTPIN(A, 11), 0); /* ETX3 */
#else
- at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
+ at91_set_B_periph(AT91_PORTPIN(A, 23), 0); /* ETX2 */
+ at91_set_B_periph(AT91_PORTPIN(A, 24), 0); /* ETX3 */
#endif
- at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
+ at91_set_B_periph(AT91_PORTPIN(A, 22), 0); /* ETXER */
#endif
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c
b/cpu/arm926ejs/at91/at91sam9261_devices.c
index 16d411f..9112ccb 100644
--- a/cpu/arm926ejs/at91/at91sam9261_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9261_devices.c
@@ -30,29 +30,29 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */
+ at91_set_a_periph(AT91_PORTPIN(C, 8), 1); /* TXD0 */
+ at91_set_a_periph(AT91_PORTPIN(C, 9), 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */
+ at91_set_a_periph(AT91_PORTPIN(C, 12), 1); /* TXD1 */
+ at91_set_a_periph(AT91_PORTPIN(C, 13), 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */
+ at91_set_a_periph(AT91_PORTPIN(C, 14), 1); /* TXD2 */
+ at91_set_a_periph(AT91_PORTPIN(C, 15), 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */
+ at91_set_a_periph(AT91_PORTPIN(A, 9), 0); /* DRXD */
+ at91_set_a_periph(AT91_PORTPIN(A, 10), 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
}
@@ -78,71 +78,71 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(A, 0), 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PORTPIN(A, 1), 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(A, 2), 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PA3, 1);
+ at91_set_a_periph(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_A_periph(AT91_PIN_PA4, 1);
+ at91_set_a_periph(AT91_PORTPIN(A, 4), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PA5, 1);
+ at91_set_a_periph(AT91_PORTPIN(A, 5), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PA6, 1);
+ at91_set_a_periph(AT91_PORTPIN(A, 6), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA4, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 4), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PA5, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 5), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PA6, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 6), 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB30, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB31, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB29, 0); /* SPI1_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(B, 30), 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PORTPIN(B, 31), 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(B, 29), 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI1);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB28, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 28), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PA24, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 24), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PA25, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 25), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PA26, 1);
+ at91_set_a_periph(AT91_PORTPIN(A, 26), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB28, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 28), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA24, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 24), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PA25, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 25), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PA26, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 26), 1);
}
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c
b/cpu/arm926ejs/at91/at91sam9263_devices.c
index f72efdf..eb56ebf 100644
--- a/cpu/arm926ejs/at91/at91sam9263_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9263_devices.c
@@ -34,29 +34,29 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 26), 1); /* TXD0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 27), 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
+ at91_set_a_periph(AT91_PORTPIN(D, 0), 1); /* TXD1 */
+ at91_set_a_periph(AT91_PORTPIN(D, 1), 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
+ at91_set_a_periph(AT91_PORTPIN(D, 2), 1); /* TXD2 */
+ at91_set_a_periph(AT91_PORTPIN(D, 3), 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
+ at91_set_a_periph(AT91_PORTPIN(C, 30), 0); /* DRXD */
+ at91_set_a_periph(AT91_PORTPIN(C, 31), 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
}
@@ -82,71 +82,71 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
- at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
- at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
+ at91_set_b_periph(AT91_PORTPIN(A, 0), 0); /* SPI0_MISO */
+ at91_set_b_periph(AT91_PORTPIN(A, 1), 0); /* SPI0_MOSI */
+ at91_set_b_periph(AT91_PORTPIN(A, 2), 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
if (cs_mask & (1 << 0)) {
- at91_set_B_periph(AT91_PIN_PA5, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 5), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PA3, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PA4, 1);
+ at91_set_b_periph(AT91_PORTPIN(A, 4), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PB11, 1);
+ at91_set_b_periph(AT91_PORTPIN(B, 11), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA5, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 5), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PA3, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 3), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PA4, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 4), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PB11, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 11), 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(B, 12), 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PORTPIN(B, 13), 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(B, 14), 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB15, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 15), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_A_periph(AT91_PIN_PB16, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 16), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PB17, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 17), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PB18, 1);
+ at91_set_a_periph(AT91_PORTPIN(B, 18), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB15, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 15), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB16, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 16), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PB17, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 17), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PB18, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 18), 1);
}
}
#endif
@@ -154,26 +154,26 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
- at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
+ at91_set_a_periph(AT91_PORTPIN(E, 21), 0); /* ETXCK_EREFCK */
+ at91_set_b_periph(AT91_PORTPIN(C, 25), 0); /* ERXDV */
+ at91_set_a_periph(AT91_PORTPIN(E, 25), 0); /* ERX0 */
+ at91_set_a_periph(AT91_PORTPIN(E, 26), 0); /* ERX1 */
+ at91_set_a_periph(AT91_PORTPIN(E, 27), 0); /* ERXER */
+ at91_set_a_periph(AT91_PORTPIN(E, 28), 0); /* ETXEN */
+ at91_set_a_periph(AT91_PORTPIN(E, 23), 0); /* ETX0 */
+ at91_set_a_periph(AT91_PORTPIN(E, 24), 0); /* ETX1 */
+ at91_set_a_periph(AT91_PORTPIN(E, 30), 0); /* EMDIO */
+ at91_set_a_periph(AT91_PORTPIN(E, 29), 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
- at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
- at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
+ at91_set_a_periph(AT91_PORTPIN(E, 22), 0); /* ECRS */
+ at91_set_b_periph(AT91_PORTPIN(C, 26), 0); /* ECOL */
+ at91_set_b_periph(AT91_PORTPIN(C, 22), 0); /* ERX2 */
+ at91_set_b_periph(AT91_PORTPIN(C, 23), 0); /* ERX3 */
+ at91_set_b_periph(AT91_PORTPIN(C, 27), 0); /* ERXCK */
+ at91_set_b_periph(AT91_PORTPIN(C, 20), 0); /* ETX2 */
+ at91_set_b_periph(AT91_PORTPIN(C, 21), 0); /* ETX3 */
+ at91_set_b_periph(AT91_PORTPIN(C, 24), 0); /* ETXER */
#endif
}
#endif
@@ -182,16 +182,16 @@ void at91_macb_hw_init(void)
void at91_uhp_hw_init(void)
{
/* Enable VBus on UHP ports */
- at91_set_gpio_output(AT91_PIN_PA21, 0);
- at91_set_gpio_output(AT91_PIN_PA24, 0);
+ at91_set_gpio_output(AT91_PORTPIN(A, 21), 0);
+ at91_set_gpio_output(AT91_PORTPIN(A, 24), 0);
}
#endif
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */
- at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */
+ at91_set_a_periph(AT91_PORTPIN(A, 13), 0); /* CAN_TX */
+ at91_set_a_periph(AT91_PORTPIN(A, 14), 1); /* CAN_RX */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN);
diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
index 98d90f2..c3a2102 100644
--- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -30,29 +30,29 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
+ at91_set_a_periph(AT91_PORTPIN(B, 19), 1); /* TXD0 */
+ at91_set_a_periph(AT91_PORTPIN(B, 18), 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
+ at91_set_a_periph(AT91_PORTPIN(B, 4), 1); /* TXD1 */
+ at91_set_a_periph(AT91_PORTPIN(B, 5), 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */
+ at91_set_a_periph(AT91_PORTPIN(D, 6), 1); /* TXD2 */
+ at91_set_a_periph(AT91_PORTPIN(D, 7), 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
+ at91_set_a_periph(AT91_PORTPIN(B, 12), 0); /* DRXD */
+ at91_set_a_periph(AT91_PORTPIN(B, 13), 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
}
@@ -78,71 +78,71 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(B, 0), 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PORTPIN(B, 1), 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(B, 2), 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB3, 0);
+ at91_set_a_periph(AT91_PORTPIN(B, 3), 0);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PB18, 0);
+ at91_set_b_periph(AT91_PORTPIN(B, 18), 0);
}
if (cs_mask & (1 << 2)) {
- at91_set_B_periph(AT91_PIN_PB19, 0);
+ at91_set_b_periph(AT91_PORTPIN(B, 19), 0);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PD27, 0);
+ at91_set_b_periph(AT91_PORTPIN(D, 27), 0);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB3, 0);
+ at91_set_gpio_output(AT91_PORTPIN(B, 3), 0);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB18, 0);
+ at91_set_gpio_output(AT91_PORTPIN(B, 18), 0);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PB19, 0);
+ at91_set_gpio_output(AT91_PORTPIN(B, 19), 0);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD27, 0);
+ at91_set_gpio_output(AT91_PORTPIN(D, 27), 0);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
- at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
- at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(B, 14), 0); /* SPI1_MISO */
+ at91_set_a_periph(AT91_PORTPIN(B, 15), 0); /* SPI1_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(B, 16), 0); /* SPI1_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PB17, 0);
+ at91_set_a_periph(AT91_PORTPIN(B, 17), 0);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PD28, 0);
+ at91_set_b_periph(AT91_PORTPIN(D, 28), 0);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PD18, 0);
+ at91_set_a_periph(AT91_PORTPIN(D, 18), 0);
}
if (cs_mask & (1 << 3)) {
- at91_set_A_periph(AT91_PIN_PD19, 0);
+ at91_set_a_periph(AT91_PORTPIN(D, 19), 0);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PB17, 0);
+ at91_set_gpio_output(AT91_PORTPIN(B, 17), 0);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PD28, 0);
+ at91_set_gpio_output(AT91_PORTPIN(D, 28), 0);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PD18, 0);
+ at91_set_gpio_output(AT91_PORTPIN(D, 18), 0);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD19, 0);
+ at91_set_gpio_output(AT91_PORTPIN(D, 19), 0);
}
}
@@ -151,25 +151,25 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
- at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
- at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
- at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
- at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
- at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
- at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
- at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
+ at91_set_a_periph(AT91_PORTPIN(A, 17), 0); /* ETXCK_EREFCK */
+ at91_set_a_periph(AT91_PORTPIN(A, 15), 0); /* ERXDV */
+ at91_set_a_periph(AT91_PORTPIN(A, 12), 0); /* ERX0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 13), 0); /* ERX1 */
+ at91_set_a_periph(AT91_PORTPIN(A, 16), 0); /* ERXER */
+ at91_set_a_periph(AT91_PORTPIN(A, 14), 0); /* ETXEN */
+ at91_set_a_periph(AT91_PORTPIN(A, 10), 0); /* ETX0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 11), 0); /* ETX1 */
+ at91_set_a_periph(AT91_PORTPIN(A, 19), 0); /* EMDIO */
+ at91_set_a_periph(AT91_PORTPIN(A, 18), 0); /* EMDC */
#ifndef CONFIG_RMII
- at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
- at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
- at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
- at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
- at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
- at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
- at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
- at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
+ at91_set_b_periph(AT91_PORTPIN(A, 29), 0); /* ECRS */
+ at91_set_b_periph(AT91_PORTPIN(A, 30), 0); /* ECOL */
+ at91_set_b_periph(AT91_PORTPIN(A, 8), 0); /* ERX2 */
+ at91_set_b_periph(AT91_PORTPIN(A, 9), 0); /* ERX3 */
+ at91_set_b_periph(AT91_PORTPIN(A, 28), 0); /* ERXCK */
+ at91_set_b_periph(AT91_PORTPIN(A, 6), 0); /* ETX2 */
+ at91_set_b_periph(AT91_PORTPIN(A, 7), 0); /* ETX3 */
+ at91_set_b_periph(AT91_PORTPIN(A, 27), 0); /* ETXER */
#endif
}
#endif
diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c
b/cpu/arm926ejs/at91/at91sam9rl_devices.c
index ebed193..9c5624a 100644
--- a/cpu/arm926ejs/at91/at91sam9rl_devices.c
+++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c
@@ -30,29 +30,29 @@
void at91_serial0_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
- at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 6), 1); /* TXD0 */
+ at91_set_a_periph(AT91_PORTPIN(A, 7), 0); /* RXD0 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0);
}
void at91_serial1_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
- at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
+ at91_set_a_periph(AT91_PORTPIN(A, 11), 1); /* TXD1 */
+ at91_set_a_periph(AT91_PORTPIN(A, 12), 0); /* RXD1 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1);
}
void at91_serial2_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
- at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
+ at91_set_a_periph(AT91_PORTPIN(A, 13), 1); /* TXD2 */
+ at91_set_a_periph(AT91_PORTPIN(A, 14), 0); /* RXD2 */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2);
}
void at91_serial3_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
- at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
+ at91_set_a_periph(AT91_PORTPIN(A, 21), 0); /* DRXD */
+ at91_set_a_periph(AT91_PORTPIN(A, 22), 1); /* DTXD */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
}
@@ -78,36 +78,36 @@ void at91_serial_hw_init(void)
#ifdef CONFIG_HAS_DATAFLASH
void at91_spi0_hw_init(unsigned long cs_mask)
{
- at91_set_A_periph(AT91_PIN_PA25, 0); /* SPI0_MISO */
- at91_set_A_periph(AT91_PIN_PA26, 0); /* SPI0_MOSI */
- at91_set_A_periph(AT91_PIN_PA27, 0); /* SPI0_SPCK */
+ at91_set_a_periph(AT91_PORTPIN(A, 25), 0); /* SPI0_MISO */
+ at91_set_a_periph(AT91_PORTPIN(A, 26), 0); /* SPI0_MOSI */
+ at91_set_a_periph(AT91_PORTPIN(A, 27), 0); /* SPI0_SPCK */
/* Enable clock */
at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_SPI);
if (cs_mask & (1 << 0)) {
- at91_set_A_periph(AT91_PIN_PA28, 1);
+ at91_set_a_periph(AT91_PORTPIN(A, 28), 1);
}
if (cs_mask & (1 << 1)) {
- at91_set_B_periph(AT91_PIN_PB7, 1);
+ at91_set_b_periph(AT91_PORTPIN(B, 7), 1);
}
if (cs_mask & (1 << 2)) {
- at91_set_A_periph(AT91_PIN_PD8, 1);
+ at91_set_a_periph(AT91_PORTPIN(D, 8), 1);
}
if (cs_mask & (1 << 3)) {
- at91_set_B_periph(AT91_PIN_PD9, 1);
+ at91_set_b_periph(AT91_PORTPIN(D, 9), 1);
}
if (cs_mask & (1 << 4)) {
- at91_set_gpio_output(AT91_PIN_PA28, 1);
+ at91_set_gpio_output(AT91_PORTPIN(A, 28), 1);
}
if (cs_mask & (1 << 5)) {
- at91_set_gpio_output(AT91_PIN_PB7, 1);
+ at91_set_gpio_output(AT91_PORTPIN(B, 7), 1);
}
if (cs_mask & (1 << 6)) {
- at91_set_gpio_output(AT91_PIN_PD8, 1);
+ at91_set_gpio_output(AT91_PORTPIN(D, 8), 1);
}
if (cs_mask & (1 << 7)) {
- at91_set_gpio_output(AT91_PIN_PD9, 1);
+ at91_set_gpio_output(AT91_PORTPIN(D, 9), 1);
}
}
#endif
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