On Thu, Dec 28, 2017 at 08:40:01PM +0530, Lokesh Vutla wrote: > DPLL DRR doesn't have an M4 divider. But the clock driver is trying > to configure M4 divider as 4(writing into a reserved register). > Fixing it by making M4 divider as -1. > > Reported-by: Steve Kipisz <s-kipi...@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvu...@ti.com>
Applied to u-boot/master, thanks! -- Tom
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